利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.021 秒)

    INSTRUCTION PROCESSING SYSTEM AND METHOD
    3.
    发明公开
    INSTRUCTION PROCESSING SYSTEM AND METHOD 审中-公开
    指令处理系统及方法

    公开(公告)号：EP2954406A1

    公开(公告)日：2015-12-16

    申请号：EP14748511.4

    申请日：2014-01-29

    申请人： Shanghai Xinhao Microelectronics Co. Ltd.

    发明人： LIN, Kenneth Chenghao

    IPC分类号： G06F9/32

    CPC分类号： G06F9/32 ,  G06F9/3804

    摘要： An instruction processing system is provided. The system includes a central processing unit (CPU), an m number of memory devices and an instruction control unit. The CPU is capable of being coupled to the m number of memory devices. Further, the CPU is configured to execute one or more instructions of the executable instructions. The m number of memory devices with different access speeds are configured to store the instructions, where m is a natural number greater than 1. The instruction control unit is configured to, based on a track address of a target instruction of a branch instruction stored in a track table, control a memory with a lower speed to provide the instruction for a memory with a higher speed.

    BUFFERING SYSTEM AND METHOD BASED ON INSTRUCTION CACHE
    4.
    发明公开
    BUFFERING SYSTEM AND METHOD BASED ON INSTRUCTION CACHE 审中-公开
    维多利亚州基金会基金会基金会BEFEHLSCACHESPEICHERS

    公开(公告)号：EP3037957A1

    公开(公告)日：2016-06-29

    申请号：EP14838463.9

    申请日：2014-08-18

    申请人： Shanghai Xinhao Microelectronics Co. Ltd.

    发明人： LIN, Kenneth Chenghao

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30145 ,  G06F9/3005 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806

    摘要： This invention provides a cache system and method based on instruction read buffer (IRB). When applied to the field of processor, it is capable of filling instructions to the instruction read buffer which can be directly accessed by processor core and the processor core outputs instruction to the processor core for execution autonomously and achieve a high cache hit rate.

    摘要翻译： 本发明提供了一种基于指令读缓冲器（IRB）的缓存系统和方法。 当应用于处理器领域时，它能够将指令填充到指令读取缓冲器中，该指令可由处理器核心直接访问，并且处理器核心自动向处理器核心输出指令以执行高速缓存命中率。

    PROCESSOR SYSTEM AND METHOD USING VARIABLE LENGTH INSTRUCTION WORD
    5.
    发明公开
    PROCESSOR SYSTEM AND METHOD USING VARIABLE LENGTH INSTRUCTION WORD 审中-公开
    VERFAHREN MIT BEFEHLSWORT MIT VARIABLERLÄNGE的PROZESSORSYSTEM

    公开(公告)号：EP3037956A1

    公开(公告)日：2016-06-29

    申请号：EP14837824.3

    申请日：2014-08-15

    申请人： Shanghai Xinhao Microelectronics Co. Ltd.

    发明人： LIN, Kenneth Chenghao

    IPC分类号： G06F9/38

    CPC分类号： G06F9/32 ,  G06F9/26 ,  G06F9/261 ,  G06F9/30032 ,  G06F9/3005 ,  G06F9/30149 ,  G06F9/382

    摘要： A variable length instruction processor system and method is provided. Before a processor core executes an instruction, the system and method applied in a processor field convert the instruction into micro-operation(s) and the micro-operation(s) can be filled into a cache system that can be directly accessed by a processor core, reducing the depth of a pipeline and improving efficiency of the pipeline.

    摘要翻译： 提供了一种可变长度指令处理器系统和方法。 在处理器核心执行指令之前，应用于处理器领域的系统和方法将指令转换为微操作，并且微操作可以被填充到可由处理器直接访问的高速缓存系统中 核心，减少管道深度，提高管道效率。

    INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD AND MEMORY SYSTEM
    6.
    发明公开
    INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD AND MEMORY SYSTEM 审中-公开
    信息处理系统，信息处理和存储系统

    公开(公告)号：EP2862088A1

    公开(公告)日：2015-04-22

    申请号：EP13804442.5

    申请日：2013-06-14

    申请人： Shanghai Xinhao Microelectronics Co. Ltd.

    发明人： LIN, Kenneth Chenghao

    IPC分类号： G06F12/08

    CPC分类号： G06F9/30058 ,  G06F9/30145 ,  G06F12/0215

    摘要： An information processing system is provided. The information processing system includes a processor used to obtain information, a memory used to store the information and output an information block based on a received address; and a scanner used to generate an address based on the current information block and to provide the address to the memory, where the current information block is the information block currently outputted from the memory. Thus, the speed for obtaining the information block by the processor (information block requested device) is further improved, and the execution speed of the processor and the information processing system is improved.

    BUFFERING SYSTEM AND METHOD BASED ON INSTRUCTION CACHE
    7.
    发明公开
    BUFFERING SYSTEM AND METHOD BASED ON INSTRUCTION CACHE 审中-公开
    PUFFERSYSTEM UND VERFAHREN AUF DER BASIS EINES BEFEHLSCACHESPEICHERS

    公开(公告)号：EP3037957A4

    公开(公告)日：2017-05-17

    申请号：EP14838463

    申请日：2014-08-18

    申请人： SHANGHAI XINHAO MICROELECTRONICS CO LTD

    发明人： LIN KENNETH CHENGHAO

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30145 ,  G06F9/3005 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806

    摘要： This invention provides a cache system and method based on instruction read buffer (IRB). When applied to the field of processor, it is capable of filling instructions to the instruction read buffer which can be directly accessed by processor core and the processor core outputs instruction to the processor core for execution autonomously and achieve a high cache hit rate.

    摘要翻译： 本发明提供了一种基于指令读缓冲区（IRB）的缓存系统和方法。 当应用于处理器领域时，能够向指令读取缓冲区填充指令，处理器核心可直接访问指令读取缓冲区，处理器核心向处理器核心输出指令以自主执行并实现高缓存命中率。