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    PACKET-BASED TIMING MEASUREMENT
    1.
    发明公开
    PACKET-BASED TIMING MEASUREMENT 审中-公开
    基于分组的时序

    公开(公告)号：EP2807785A1

    公开(公告)日：2014-12-03

    申请号：EP12852168.9

    申请日：2012-11-16

    申请人： Vitesse Semiconductor Corporation

    发明人： KRISTOFFERSEN, Arne ,  TERSTRUP, Morten

    IPC分类号： H04L7/04 ,  H04L12/70

    CPC分类号： H04J3/0658 ,  H04J3/0667 ,  H04J3/0697 ,  H04L43/0858

    摘要： A slave communication device may transmit a packet to the master communication device, with the packet including a transmission time field and a correction field. The transmission time field may contain a value indicative of an approximate time of transmission of the packet by the slave communication device, and the correction field may contain a value indicative of a difference between the approximate time of transmission and an actual time of transmission of the packet by the slave communication device.

    Timestamp predictor for packets over a synchronous protocol
    4.
    发明公开
    Timestamp predictor for packets over a synchronous protocol 审中-公开
    ZeetstempelvorhersagefürPaketeüberein同步Protokoll

    公开(公告)号：EP2437416A2

    公开(公告)日：2012-04-04

    申请号：EP11183242.4

    申请日：2011-09-29

    申请人： Vitesse Semiconductor Corporation

    发明人： Swartzentruber, Ron ,  Rao, Ganesh

    IPC分类号： H04J3/06 ,  H04L12/56

    CPC分类号： H04L43/106 ,  H04J3/0682 ,  H04J3/0685 ,  H04J3/0691 ,  H04J3/0697 ,  H04J2203/0082 ,  H04L7/0091 ,  H04L41/147 ,  H04L43/0852

    摘要： A physical layer communication device (PHY) transmits and receives signal to and from a communication link using a synchronous protocol. The PHY communicates with a higher-layer device using a packet protocol. Timestamp values contained in timing-related messages in some packets are written or modified by the PHY. Delays incurred in transmitting and receiving the packets are predicted and used in setting the timestamp values.

    摘要翻译： 物理层通信设备（PHY）使用同步协议向通信链路发送信号和从通信链路接收信号。 PHY使用分组协议与较高层设备进行通信。 某些数据包中定时相关消息中包含的时间戳值由PHY写入或修改。 在发送和接收数据包时发生的延迟被预测并用于设置时间戳值。

    METHOD AND CIRCUITRY FOR HIGH SPEED BUFFERING OF CLOCK SIGNALS
    7.
    发明公开
    METHOD AND CIRCUITRY FOR HIGH SPEED BUFFERING OF CLOCK SIGNALS 有权
    方法和电路装置，高速BUFFERING时钟信号

    公开(公告)号：EP1110321A1

    公开(公告)日：2001-06-27

    申请号：EP00945082.6

    申请日：2000-06-30

    申请人： Vitesse Semiconductor Corporation

    发明人： WARWAR, Greg

    IPC分类号： H03K19/017 ,  H03K19/0185

    CPC分类号： H03K19/018514 ,  H03K19/01721

    摘要： A high bandwidth clock buffer, including a steering circuit, significantly increases the maximum frequency at which CMOS technology can be used to perform high-speed logic functions. In particular, the clock buffer includes a steering circuit for enhancing a voltage follower stage. The steering circuit includes steering transistors positioned between voltage follower transistors and constant current sources. The steering circuit switches all or substantially all of the current from both of the constant current sources through whichever of the two voltage follower transistors is being pulled low, thus doubling the amount of current that is available for slewing when the output is being pulled low. At the same time, since the voltage follower transistor that is being pulled high no longer has to source the constant current I0, the effective maximum current that can be supplied to charge up the load capacitance is increased by approximately I0. The clock buffer provides a higher unity gain bandwidth than a standard CML buffer, while maintaining a well controlled delay which will track other logic gates.

    High speed cross point switch routing circuit with word-synchronous serial back plane
    8.
    发明公开
    High speed cross point switch routing circuit with word-synchronous serial back plane 有权
    Leitweglenkungschaltung einer Schaltmatrix mit hoher Geschwindigkeit und mit Flu kontrolle

    公开(公告)号：EP0978968A2

    公开(公告)日：2000-02-09

    申请号：EP99250262.5

    申请日：1999-08-03

    申请人： Vitesse Semiconductor Corporation

    发明人： Mullaney, John P. ,  Lee, Gary M.

    IPC分类号： H04L12/56 ,  H04Q11/04

    CPC分类号： H04L12/5601 ,  H04J3/0685 ,  H04L7/04 ,  H04L49/1576 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5674 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5684 ,  H04Q11/0478

    摘要： An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

    摘要翻译： 异步串行交叉点开关与多个收发器电路中的每一个字字同步。 交叉点开关电路产生主位时钟和主字时钟信号。 收发器电路使用时钟和数据恢复电路从输入的高速串行数据流中恢复主位时钟信号。 恢复的位时钟信号用作定时信号，数据被串行化并发送到交叉点开关电路。 发送到开关电路的数据流被锁定到主位时钟信号，使得串行数据流仅需要用数据恢复电路进行相位调整。 为了恢复字定时，开关电路在链接初始化期间向收发器发出对准字。 收发器执行字对齐并建立本地字锁。 然后使用本地字时钟将对准字重新发布到开关电路。 开关电路将接收的字时钟的边界与主字时钟进行比较，如果未对准，收发器将其发送的字移位一位，然后重试。 必要的边缘转换密度由开销比特提供，开销比特也指示在收发机和开关电路之间确定的特殊命令字。 流量控制信息使用开销比特从接收收发器路由到发送收发器，以便断言准备接收或不准备接收的流量控制信号。 开销比特还提供关于连接请求和其他信息的信息。

    PACKET PROTOCOL PROCESSING WITH PRECISION TIMING PROTOCOL SUPPORT
    9.
    发明公开
    PACKET PROTOCOL PROCESSING WITH PRECISION TIMING PROTOCOL SUPPORT 审中-公开
    包装协议处理精确时间地点的协议支持

    公开(公告)号：EP2589178A2

    公开(公告)日：2013-05-08

    申请号：EP11801427.3

    申请日：2011-06-30

    申请人： Vitesse Semiconductor Corporation

    发明人： SWARTZENTRUBER, Ron ,  LOPOULOS, Wiliam, D.

    IPC分类号： H04L7/00 ,  H04L12/56 ,  H04L29/06

    CPC分类号： H04J3/0661 ,  H04L7/042 ,  H04L69/22 ,  H04L69/28

    摘要： Device and methods determine timing parameters and associated timing actions from timing messages in communication packets. The timing messages may be encapsulated with a plurality of communication protocols. An example timing message may be an IEEE 1588 timing message encapsulated in an Internet protocol packet encapsulated in an Ethernet protocol packet. The protocols are matched in classifier blocks by comparing portions of the packet to bit values or ranges of values. Operation of other than the first classifier block depends on results of matching in the preceding block by using offset values passed between blocks that indicate starting points for the matching. The final classifier block matches values in timing messages to identify timing parameters and associated timing actions in the message.