-
公开(公告)号：EP2649463A4
公开(公告)日：2017-10-25
申请号：EP11847860
申请日：2011-12-09
发明人： BRANDORFF ALEXANDER
CPC分类号： G01R1/07342 , G01R1/06733 , G01R31/2886
摘要： A probe card assembly for testing circuit boards is disclosed. In some embodiments, the assembly includes the following: a multi-layered dielectric plate aligned with an integrated circuit, the integrated circuit having on its surface a first plurality of electrical contacts arranged in a pattern, the dielectric plate having arrayed upon its surface a second plurality of electrical contacts arranged in a pattern substantially matching the first plurality of electrical contacts; a nanotube interposer interposed between the dielectric plate and the integrated circuit, the nanotube interposer having compliant carbon nanotubes that are arranged to match the pattern of electrical contacts on the integrated circuit and the dielectric plate; and a plurality of vertical probes arrayed upon the nanotube interposer and joined with the nanotubes, the vertical probes making electrical contact with the first plurality of electrical contacts and the second plurality of electrical contacts via the nanotubes.
-
公开(公告)号：EP2649463A1
公开(公告)日：2013-10-16
申请号：EP11847860.1
申请日：2011-12-09
发明人： BRANDORFF, Alexander
IPC分类号： G01R31/26
CPC分类号： G01R1/07342 , G01R1/06733 , G01R31/2886
摘要： A probe card assembly for testing circuit boards is disclosed. In some embodiments, the assembly includes the following: a multi-layered dielectric plate aligned with an integrated circuit, the integrated circuit having on its surface a first plurality of electrical contacts arranged in a pattern, the dielectric plate having arrayed upon its surface a second plurality of electrical contacts arranged in a pattern substantially matching the first plurality of electrical contacts; a nanotube interposer interposed between the dielectric plate and the integrated circuit, the nanotube interposer having compliant carbon nanotubes that are arranged to match the pattern of electrical contacts on the integrated circuit and the dielectric plate; and a plurality of vertical probes arrayed upon the nanotube interposer and joined with the nanotubes, the vertical probes making electrical contact with the first plurality of electrical contacts and the second plurality of electrical contacts via the nanotubes.
-
公开(公告)号：EP2329502A1
公开(公告)日：2011-06-08
申请号：EP09817037.6
申请日：2009-09-29
发明人： BRANDORFF, Alexander
IPC分类号： G21K7/00
摘要： Methods of fabricating a plurality of carbon nanotube-bundle probes on a substrate are disclosed. In some embodiments, the method includes the following: providing a substrate having a top surface and a bottom surface; forming an array of electrically conductive pads on the top surface, the array of electrically conductive pads being formed to mirror an array of pads on an integrated circuit that is to be tested; applying a catalyst for promoting growth of carbon nanotubes on each of the array of electrically conductive pads; heating the substrate in a carbon-rich environment thereby growing nanotubes extending upwardly from each of the array of electrically conductive pads and above the top surface of the substrate thereby forming a plurality of carbon nanotube-bundle probes extending upwardly above the top surface of the substrate; and capping each of the plurality of carbon nanotube-bundle probes with an electrically conductive material.
-
公开(公告)号：EP1194784B1
公开(公告)日：2008-08-13
申请号：EP01914572.1
申请日：2001-02-28
IPC分类号： G01R1/073
CPC分类号： G01R1/07314 , G01R1/07357 , G01R3/00
摘要： An improved vertical pin probing device is constructed with a housing with spaced upper (48) and lower (50) spacers of Invar3, each having a thin sheet of silicon nitride ceramic material (56, 58) held in a window in the spacer by adhesive. The sheets of silicon nitride have laser-drilled matching patterns of holes (60) supporting probe pins (64) and insulating the probe pins from the housing. The Invar spacers and silicon nitride ceramic sheets have coefficients of thermal expansion closely matching that of the silicon chip being probed, so that the probing device compensates for temperature variations over a large range of probing temperatures.
-
公开(公告)号：EP1740963A2
公开(公告)日：2007-01-10
申请号：EP05746253.3
申请日：2005-03-30
IPC分类号： G01R31/02
CPC分类号： G01R31/31905 , G01R1/06705 , G01R1/07342 , G01R31/2635
摘要： A probe head for testing the properties of a semiconducting device (10) under test including a dielectric film (24) supporting at least one semiconducting device (10) under test with a support frame (26) tautly supporting the dielectric film (24). A first support (40) positions a first probe (28) for electrically contacting a first side (16) of the semiconducting device (10) under test and a second support (34), having a actuator to move a second probe (30) between a first position (P1) and a second position (P2), positions second probe (30) with the second position (P2) being for electrically contacting an opposing second side (18) of the semiconductor device under test.
-
公开(公告)号：EP1692529A2
公开(公告)日：2006-08-23
申请号：EP04810930.0
申请日：2004-11-12
发明人： BRANDORFF, Alexander
IPC分类号： G01R31/02
CPC分类号： G01R31/2887 , G01R1/0735 , G01R1/07357 , G01R1/07371 , G01R3/00
摘要： An upper die portion (36) of a die head for a aligning probe pins (14) in first array of first micro-holes (18) formed in lower die portion (12) of the die head, which generally includes a spacer portion (38), a support frame (40), and first and second assembly aid films (42) and (44), respectively. Spacer portion (38) is adapted to contact lower die portion (12). First assembly aid film (42) is typically positioned between second surface (48) and support frame (40) and includes a second array of second micro-holes (50) adapted to receive probe pins (14). Second assembly aid film (44) generally is in contact or close proximity to first assembly aid film (42) and has a third array of third micro-holes (52) adapted to receive prove pins (14). Second array of second micro-holes (50) and third array of third micro-holes (52) are patterned to align with one another but are both offset with first array of first micro-holes (18) by approximately the lateral distance between probe tip (20) and probe head (28).
-
公开(公告)号：EP1356307A1
公开(公告)日：2003-10-29
申请号：EP02709234.5
申请日：2002-01-30
IPC分类号： G01R31/06
CPC分类号： G01R3/00 , G01R1/07307
摘要： A probe head assembly (66) for use in a vertical pin probing device of the type used to electrically test integrated circuit devices has a metallic spacer (74, 76) portion formed from a plurality of laminated metallic layers (74a-74e, 76a-76e). The laminated metallic layers (74a-74e, 76a-76e) are formed from a low coefficient of thermal expansion metal, such as Invar, a 36 % nickel-64 % iron alloy. By orienting the metallic grains of the laminated metal layers (74a-74e, 76a-76e) to be off-set from the orientation of metallic grains of adjacent foil layers (74a-74e, 76a-76e), increased strength and flatness is achieved.
-
公开(公告)号：EP1685415A2
公开(公告)日：2006-08-02
申请号：EP04796027.3
申请日：2004-10-22
CPC分类号： G01R3/00 , G01R1/06744 , Y10T29/49155
摘要： A method of manufacturing a probe test head for testing of semiconductor integrated circuits includes: defining shapes of a plurality of probes (81) as one or more masks (73); a step for fabricating the plurality of probes using the mask (73); and disposing the plurality of probes (81) through corresponding holes in a first die (42) and a second die (44). The step for fabricating the plurality of probes (81) may include one of photo-etching and photo-defined electroforming.
-
公开(公告)号：EP1441231A1
公开(公告)日：2004-07-28
申请号：EP04000617.3
申请日：2004-01-14
摘要： An improved device (10) for cleaning probe pins (62) of a probe head assembly (60) is presented. The device includes a first holding plate (20), a second holding plate (30) and a cleaning cartridge (40). The first holding plate secures the probe head assembly. The second holding plate secures the cleaning cartridge in proximity to the first holding plate. The cleaning cartridge has a chamber (42). The chamber includes a cleaning solution (44) and an absorbent pad (46) located therein. The absorbent pad is saturated with the cleaning solution and prevents leakage of the cleaning solution out of the chamber. During cleaning operations, the first holding plate is positioned about the second holding plate such that the probe pins of a probe head extend into and contact the absorbent pad in the chamber. Once contact is established, the cleaning solution acts upon the probe pin tips to remove unwanted debris. A depth of penetration of the pins into the pad is controlled by a surface (48) of the cartridge.
摘要翻译： 提出了用于清洁探针头组件（60）的探针（62）的改进的装置（10）。 该装置包括第一保持板（20），第二保持板（30）和清洁盒（40）。 第一保持板固定探针头组件。 第二保持板将清洁带固定在第一固定板附近。 清洁带具有室（42）。 该室包括清洁溶液（44）和位于其中的吸收垫（46）。 吸收垫被清洁溶液饱和，并防止清洁溶液从室中泄漏出来。 在清洁操作期间，第一保持板围绕第二保持板定位，使得探针头的探针插入腔室中的吸收垫并进入其中。 一旦建立接触，清洁溶液将作用在探针针尖上，以除去不需要的碎屑。 销钉穿入垫的深度由盒的表面（48）控制。
-
公开(公告)号：EP0127295A1
公开(公告)日：1984-12-05
申请号：EP84302479.5
申请日：1984-04-11
发明人： Evans, Arthur
IPC分类号： G01R1/073
CPC分类号： G01R1/07342
摘要： A test probe assembly for checking an integrated circuit chip before terminal leads are applied to the contacts thereof which are deployed on the chip in a common plane. The assembly includes a planar insulation card (T 10 ) provided with a port (T 11 ) and having a printed circuit thereon whose traces are connected to a plurality of test terminals (T 16 ) connectable to external testing equipment. Surrounding the port (T 11 ) and bonded to the card is a mounting ring of dielectric material having a flat face on which is supported a radial array of fine wires (T 17 ). These are maintained in their assigned positions by a layer of dielectric material adherent to the face, the wires (T 12 ) being embedded in the layer. The wires (T 12 ) cantilever across the port (T 11 ) and converge toward the central region thereof below which is disposed the chip (T 20 ) to be tested, the leading ends of the wires (T 12 ) being double bent to define obtuse angle needles whose tips engage the respective contacts on the chip (T 20 ). The trailing ends of the wire (T 12 ) which diverge outwardly from the ring are soldered to the traces whereby each needle is connected to a respective test terminal (T 16 ).
摘要翻译： 用于在端子引线之前检查集成电路芯片的测试探针组件被施加到在公共平面中部署在芯片上的触点。 组件包括设置有端口（T11）并且在其上具有印刷电路的平面绝缘卡（T10），其迹线连接到可连接到外部测试设备的多个测试端子（T16）。 围绕端口（T11）并且结合到卡上的是具有平坦表面的电介质材料的安装环，在该安装环上支撑有细小导线（T17）的径向阵列。 这些通过一层与介质粘附的电介质材料保持在其分配的位置，电线（T12）被嵌入在该层中。 电线（T12）悬臂穿过端口（T11）并且朝向其中心区域会聚，在其中方设置待测试的芯片（T20），电线（T12）的前端被双重弯曲以限定钝角针， 尖端接合芯片上的各个触点（T20）。 从环向外发散的线（T12）的尾端被焊接到轨迹，由此每个针连接到相应的测试端（T16）。
-
-
-
-
-
-
-
-
-
搜索结果
22 条记录 (耗时 0.01 秒)
