公开(公告)号：EP1661177B1

公开(公告)日：2009-08-26

申请号：EP04816840.5

申请日：2004-08-31

申请人： ADVANCED MICRO DEVICES, INC.

发明人： XIANG, Qi ,  ZHONG, Huicai ,  GOO, Jung-Suk ,  HOLBROOK, Allison, Kay ,  JEON, Joong, S. ,  KLUTH, George, Jonathan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).

公开(公告)号：EP1661177A2

公开(公告)日：2006-05-31

申请号：EP04816840.5

申请日：2004-08-31

申请人： ADVANCED MICRO DEVICES, INC.

发明人： XIANG, Qi ,  ZHONG, Huicai ,  GOO, Jung-Suk ,  HOLBROOK, Allison, Kay ,  JEON, Joong, S. ,  KLUTH, George, Jonathan

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： According to one exemplary embodiment, a method for integrating first (206) and second metal layers (208) on a substrate (202) to form a dual metal NMOS gate (226) and PMOS gate (228) comprises depositing (150) a dielectric layer (204) over an NMOS region (210) and a PMOS region (212) of the substrate (202). The method further comprises depositing (150) the first metal layer (206) over dielectric layer (204). The method further comprises depositing (150) the second metal layer (208) over the first metal layer (206). The method further comprises implanting (152) nitrogen in the NMOS region (210) of substrate (202) and converting (154) a first portion of the first metal layer (206) into a metal oxide layer (220) and converting a second portion of the first metal layer (206) into metal nitride layer (218). The method further comprises forming (156) the NMOS gate (226) and the PMOS gate (228), where the NMOS gate (226) comprises a segment (234) of metal nitride layer (218) and the PMOS gate (228) comprises a segment (242) of the metal oxide layer (220).

公开(公告)号：EP1342260A1

公开(公告)日：2003-09-10

申请号：EP01990802.9

申请日：2001-12-03

申请人： ADVANCED MICRO DEVICES INC.

发明人： PATON, Eric, N. ,  ADEM, Ercan ,  BERTRAND, Jacques, J. ,  BESSER, Paul, R. ,  BUYNOSKI, Matthew, S. ,  FOSTER, John, Clayton ,  KING, Paul, L. ,  KLUTH, George, Jonathan ,  NGO, Minh, Van ,  WOO, Christy, Mei-Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4933

摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide regions (56, 58) and dielectric (60) are reacted at a prescribed temperature to form at least one low resistance silicideregion (64, 66) and process the dielectri c layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between silicide region (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).