-
1.发明公开COPPER INTERCONNECTS WITH IMPROVED ELECTROMIGRATION RESISTANCE AND LOW RESISTIVITY 审中-公开具有改进的电迁移特性 - 低电阻铜导线
公开(公告)号：EP1309993A1
公开(公告)日：2003-05-14
申请号：EP01923120.8
申请日：2001-04-03
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Copper interconnects are formed by depositing substantially pure copper (30) into the lower portion of an interconnect opening (24). The upper portion of the interconnect opening (24) is then filled with doped copper (32) followed by a planarization process. The resulting copper interconnect exhibits reduced electromigration while maintaining low overall resistivity.
-
2.发明公开CHEMICAL-MECHANICAL POLISHING SLURRY FORMULATION AND METHOD FOR TUNGSTEN AND TITANIUM THIN FILMS 失效化学机械浆配方为薄膜钨和TITAN抛光方法
公开(公告)号：EP0970156A1
公开(公告)日：2000-01-12
申请号：EP98913168.5
申请日：1998-03-26
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/3212
摘要： A polishing slurry composition and its method of making for planarization of silicon semiconductor wafers by chemical mechanical polishing of the wafer. A slurry formulation utilizing a ferric salt tungsten oxidizer, an ammonium persulfate titanium oxidizer, a fatty acid suspension agent, alumina particles with a small diameter and tight diameter range, coated with a solubility coating, and a chemical stabilizer, provides high tungsten and titanium polish rates with high selectivity to silicon dioxide, and good oxide defectivity for use in tungsten local interconnect applications. A method for making a tungsten slurry includes first thoroughly blending small diameter alumina particles with a tight diameter range in an aqueous concentrate with a suspension agent, then mixing with water and oxidizers. Ferric salt tungsten slurries made by this method provide excellent tungsten polish characteristics for via plug and local interconnect applications.
-
3.发明授权CHEMICAL-MECHANICAL POLISHING SLURRY FORMULATION AND METHOD FOR TUNGSTEN AND TITANIUM THIN FILMS 失效化学机械浆配方为薄膜钨和TITAN抛光方法
公开(公告)号：EP0970156B1
公开(公告)日：2003-09-24
申请号：EP98913168.5
申请日：1998-03-26
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/3212
-
4.发明公开METHOD OF FORMING NICKEL SILICIDE USING A ONE-STEP RAPID THERMAL ANNEAL PROCESS AND BACKEND PROCESSING 审中-公开用于生产镍硅化物足下，快速热处理工艺BACKEND
公开(公告)号：EP1342260A1
公开(公告)日：2003-09-10
申请号：EP01990802.9
申请日：2001-12-03
发明人： PATON, Eric, N. , ADEM, Ercan , BERTRAND, Jacques, J. , BESSER, Paul, R. , BUYNOSKI, Matthew, S. , FOSTER, John, Clayton , KING, Paul, L. , KLUTH, George, Jonathan , NGO, Minh, Van , WOO, Christy, Mei-Chu
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide regions (56, 58) and dielectric (60) are reacted at a prescribed temperature to form at least one low resistance silicideregion (64, 66) and process the dielectri c layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between silicide region (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).
-
公开(公告)号：EP1327261A1
公开(公告)日：2003-07-16
申请号：EP01977411.6
申请日：2001-10-02
IPC分类号： H01L21/336
CPC分类号： H01L29/665 , H01L29/6659
摘要： Bridging between nickel silicide layers (30) on a gate electrode (21) and source/drain regions (26) along silicon nitride-sidewall spacers (24) is prevented by forming a relatively thick silicon oxide liner (23) on the side surfaces of the gate electrode (21) and adjacent surface of the semiconductor substrate (20) before forming the silicon nitride sidewall spacers (24) thereon. Embodiments include forming a silicon dioxide liner (23) at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers (24) thereon.
-
6.发明公开
公开(公告)号：EP0792515A1
公开(公告)日：1997-09-03
申请号：EP95938941.0
申请日：1995-10-23
CPC分类号： H01L21/3212 , H01L21/321
摘要： A tungsten chemical-mechanical polishing slurry formulated from small median diameter abrasive particles having a very tight diameter variation and by thoroughly premixing the abrasive with a surfactant suspension agent before combining the oxidizer.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.012 秒)
