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7 条记录 (耗时 0.009 秒)

    TTL Buffer circuit
    2.
    发明公开
    TTL Buffer circuit 失效
    TTL缓冲电路

    公开(公告)号：EP0250007A3

    公开(公告)日：1989-12-27

    申请号：EP87200416.3

    申请日：1987-03-06

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Tavana, Danash M. ,  Wong, Sing Y.

    IPC分类号： H03K19/088 ,  H03K19/013

    CPC分类号： H03K19/0136 ,  H03K19/088

    摘要： A TTL buffer circuit (30) which is switched by an increasing or decreasing voltage input signal (Ii) at the same threshold, and which switches at increased speed. A bleed transistor (Q6) allows the phase splitter transistor base to begin charging before the bleed transistor (Q6) turns on. While the phase splitter transistor (Q3) is on, the bleed transistor current is limited to avoid interfering with operation of the phase splitter transistor (Q3). When the phase splitter control lead current is cut off, the phase splitter base capacitance is discharged rapidly through the bleed transistor (Q6), at the end of which the phase splitter and bleed transistors (Q3, Q6) stop conducting.

    TTL Buffer circuit
    3.
    发明公开
    TTL Buffer circuit 失效
    TTL-Pufferschaltung。

    公开(公告)号：EP0250007A2

    公开(公告)日：1987-12-23

    申请号：EP87200416.3

    申请日：1987-03-06

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Tavana, Danash M. ,  Wong, Sing Y.

    IPC分类号： H03K19/088 ,  H03K19/013

    CPC分类号： H03K19/0136 ,  H03K19/088

    摘要： A TTL buffer circuit (30) which is switched by an increasing or decreasing voltage input signal (Ii) at the same threshold, and which switches at increased speed. A bleed transistor (Q6) allows the phase splitter transistor base to begin charging before the bleed transistor (Q6) turns on. While the phase splitter transistor (Q3) is on, the bleed transistor current is limited to avoid interfering with operation of the phase splitter transistor (Q3). When the phase splitter control lead current is cut off, the phase splitter base capacitance is discharged rapidly through the bleed transistor (Q6), at the end of which the phase splitter and bleed transistors (Q3, Q6) stop conducting.

    摘要翻译： TTL缓冲电路（30），其以相同阈值的增加或减少的电压输入信号（Ii）切换，并以增加的速度切换。 放电晶体管（Q6）允许分相晶体管基极在放电晶体管（Q6）导通之前开始充电。 当分相晶体管（Q3）导通时，放电晶体管电流受到限制，以避免干扰分相晶体管（Q3）的工作。 当分相器控制引线电流被切断时，相分离器基极电容通过放电晶体管（Q6）快速放电，其中分相器和放电晶体管（Q3，Q6）停止导通。

    Programmable array logic cell
    4.
    发明公开
    Programmable array logic cell 失效
    Programmierbare Array-Logik-Zelle。

    公开(公告)号：EP0245884A2

    公开(公告)日：1987-11-19

    申请号：EP87200415.5

    申请日：1987-03-06

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Birkner, John M. ,  Tavana, Danesh M. ,  Chan, Andrew K. ,  Wong, Sing Y.

    IPC分类号： H03K19/177

    CPC分类号： H03K3/037

    摘要： A programmable array logic cell (60) including a sum-of- products array having a single OR gate (70) for providing a sum signal, and including an XOR gate (80) for combining the sum signal with a product signal provided by an AND gate (78) from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

    摘要翻译： 一种可编程阵列逻辑单元（60），包括具有用于提供和信号的单或门（70）的积和积数组，并且包括用于将和信号与由 AND门（78）从选定的阵列输入和/或反馈信号。 产品信号可以是用于JK触发器配置的先前状态输出信号Q，或用于可编程输出信号极性的其他配置的强制高或低信号。

    Multiple programmable initialize words in a programmable read only memory
    6.
    发明公开
    Multiple programmable initialize words in a programmable read only memory 失效
    Eine Vielzahl vonInitialisierungswörternin einem programmierbaren Festwertspeicher。

    公开(公告)号：EP0175420A2

    公开(公告)日：1986-03-26

    申请号：EP85201461.2

    申请日：1985-09-13

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Wong, Sing Y. ,  Chen, Johnny

    IPC分类号： G11C17/00

    CPC分类号： G11C7/20 ,  G11C17/14

    摘要： in accordance with this invention, a programmable read-only memory (30) is provided which is capable of storing a plurality of initialize words. The memory includes an initialize input lead (9) and appropriate addressing circuitry (7) so that when the appropriate initialize input signal is placed on the initialize input lead, one of several pre-programmed initialize words is placed in the output register (6) of the programmable read-only memory. The word that is placed in the output register is selected according to signals applied to selected address input leads (A o through A3) of the programmable read-only memory. The number of address input signals utilized to determine which initialize word is placed in the output register of the programmable read-only memory is a selected subset of the available address input signals provided to the memory.
    The described embodiment provides sixteen initialize words using a minimum number of components. The sixteen data words are stored in an additional row (12) of the programmable array which contains the memory's normally addressable data words. Because the initialize word circuit (12) is configured as an extra row of the programmable array, the initialize word occupies less chip area than a conventional initialize word circuit. In addition, fewer components are necessary to implement an initialize word construction according to this invention because the inherent selection circuitry of the programmable array is used rather than circuitry which deselects the normal data word provided by the programmable array.

    摘要翻译： 根据本发明，提供一种能够存储多个初始化字的可编程只读存储器（30）。 存储器包括初始化输入引线（9）和适当的寻址电路（7），使得当适当的初始化输入信号被放置在初始化输入引线上时，几个预编程的初始化字之一被放置在输出寄存器（6）中， 的可编程只读存储器。 根据施加到可编程只读存储器的选定地址输入引脚（A0至A3）的信号，选择放置在输出寄存器中的字。 用于确定哪个初始化字被放置在可编程只读存储器的输出寄存器中的地址输入信号的数量是在存储器中提供的可用地址输入信号的选定子集。 所描述的实施例使用最少数量的组件来提供十​​六个初始化单词。 16个数据字被存储在可编程阵列的附加行（12）中，其包含存储器通常可寻址的数据字。 由于初始化字电路（12）被配置为可编程阵列的额外行，所以初始化字占用比常规初始化字电路更少的码片区域。 此外，由于使用可编程阵列的固有选择电路而不是使可取消选择由可编程阵列提供的正常数据字的电路，因此根据本发明实现初始化字构造所需的部件较少。