利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

2 条记录 (耗时 0.008 秒)

    Programmable logic device including multipliers and configurations thereof to reduce resource utilization
    1.
    发明公开
    Programmable logic device including multipliers and configurations thereof to reduce resource utilization 有权
    用乘法器和配置的可编程逻辑电路，以避免资源的磨损

    公开(公告)号：EP1294094A2

    公开(公告)日：2003-03-19

    申请号：EP02256303.5

    申请日：2002-09-11

    申请人： Altera Corporation

    发明人： Langhammer, Martin, c/o Altera Corporation ,  Hwang, Chiao Kai, c/o Altera Corporation ,  Starr, Gregory, c/o Altera Corporation

    IPC分类号： H03K17/00

    CPC分类号： H03K19/17744 ,  G06F7/523 ,  G06F2207/3816 ,  H03K19/17728 ,  H03K19/17732

    摘要： In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

    摘要翻译： 在具有专用器电路的可编程逻辑器件，一些扫描链寄存器的通常用于测试位于乘法器的相邻输入寄存器装置。 这些扫描链寄存器相与的输入寄存器，可与1和0的模板下载。 这允许，E. G.，如果装载有零点和剩余位的至少显著位被装入那些子集乘法。 乘法器优选地布置在与其它组分，色块：如加法器，确实允许它们被配置为有限脉冲响应（FIR）滤波器。 在寻求配置中，扫描链寄存器可以用来加载滤波器系数避免使用的设备的稀缺的逻辑和路由资源。