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    SYSTEM FOR PERFORMING ARITHMETIC OPERATIONS WITH SINGLE OR DOUBLE PRECISION
    2.
    发明公开
    SYSTEM FOR PERFORMING ARITHMETIC OPERATIONS WITH SINGLE OR DOUBLE PRECISION 失效
    电路是否执行算术运算单或双精度

    公开(公告)号：EP0823083A1

    公开(公告)日：1998-02-11

    申请号：EP97914968.0

    申请日：1997-02-27

    申请人： ATMEL CORPORATION

    发明人： MUWAFI, Jumana, A. ,  TOURIGUIAN, Mihran

    IPC分类号： G06F7

    CPC分类号： G06F7/48 ,  G06F2207/3816 ,  G06F2207/3892

    摘要： An arithmetic manipulation unit (AMU) (Fig. 6) performs arithmetic operations on N-bit words in a single precision mode and on 2N-bit words in a double precision mode. Preferably, the AMU performs a double precision operation in only two pipelined cycles: a first cycle generating a first 2N-bit operand by concatenating two N-bit parts by means of a sign extension unit (42) and multiplexer (MY) (Fig. 7) and loading the operand to an output register (46); and a second cycle in which a second 2N-bit operand is generated (from a second pair of N-bit parts), the first operand is fed back from the output register, and an arithmetic operation is performed on the two operands by an arithmetic logic unit (ALU 44). A system (Fig. 1) including such an AMU circuit preferably also includes a multi-port memory (6) and a memory management unit (MMU 3; Fig. 8) using address pointers (r0-r7) to fetch two N-bit words from the memory in a single cycle.

    Method and apparatus for multiplying a plurality of numbers
    3.
    发明公开
    Method and apparatus for multiplying a plurality of numbers 失效
    用于多重数字的方法和装置。

    公开(公告)号：EP0619542A3

    公开(公告)日：1995-09-27

    申请号：EP94302057.8

    申请日：1994-03-22

    申请人： ADVANCED MICRO DEVICES INC.

    发明人： Asghar, Safdar M. ,  Mondul, Donald D.

    IPC分类号： G06F7/52 ,  G06F7/544

    CPC分类号： G06F7/523 ,  G06F7/5235 ,  G06F7/5324 ,  G06F2207/3816

    摘要： A method and apparatus for determining the product of a plurality of numbers are disclosed. The preferred embodiment of the method comprises the steps of : (1) determining a plurality of respective partial products for each pair-combination of a first number's digits and a second number's digits ; (2) providing a register having a plurality of register cells, each having a hierarchical significance; (3) accumulating selected of the respective partial products to produce accumulated values in specified of the register cells according to the following relationships: P m,n ―[accumulates in]→ r x ; x=(m+n)-1, where "P m,n " represents the respective partial product ; "m" represents the first number's significance (m = 1, 2, ...); "n" represents the second number's significance (n = 1, 2, ...); and "r x " represents a specified register cell having significance "x" ; (4) sequentially effecting a shifting accumulation operation comprising shifting specific digits of the accumulated value stored in a lesser-significant register cell to the next-higher-significant register cell containing an accumulated value, and adding the specific digits to the accumulated value stored in the next-higher-significant register cell as least-significant digits between significance-adjacent register cells from the least-significant register cell to the most-significant register cell ; (5) iteratively applying the contents of the register to repeat steps (1) through (4) with a succeeding next number until all of the plurality of new numbers have been employed by the method and (6) shifting the contents of the register from the register.

    Serial digital signal processing circuitry
    7.
    发明公开
    Serial digital signal processing circuitry 失效
    处理电路，用于串行数字信号。

    公开(公告)号：EP0238300A2

    公开(公告)日：1987-09-23

    申请号：EP87302260.2

    申请日：1987-03-17

    申请人： RCA Thomson Licensing Corporation

    发明人： McClary, Dennis Roy ,  Dieterich, Charles Benjamin

    IPC分类号： G06F5/06 ,  G06F7/48

    CPC分类号： G06F5/08 ,  G06F7/48 ,  G06F7/49994 ,  G06F2207/3816

    摘要： A serial-bit digital processing system uses registers and latches to synchronize samples and justify sign-bits. Nominally each processing block in the system includes a sign extend register (16) preceding an arithmetic element (18) and an output register (20) following the arithmetic element. Input registers of one arithmetic element may merge with output registers of the preceding arithmetic element. The sign extend registers include a serially coupled latch which is selectively controlled to pass serial sample bits or to replicate the sign bit. The respective registers are clocked with one of two clock signals (CLOCKN, CLOCKP) having different numbers of pulses per sample period and the length of the respective registers are selected so that at the terminus of each sample period the bits of each sample in the processing system are appropriately justified.

    FLOATING POINT UNIT WITH SUPPORT FOR VARIABLE LENGTH NUMBERS
    8.
    发明公开
    FLOATING POINT UNIT WITH SUPPORT FOR VARIABLE LENGTH NUMBERS 审中-公开
    GLEITKOMMAININHEIT MITUNTERSTÜTZUNGFÜRZAHLEN MIT VARIABLERLÄNGE

    公开(公告)号：EP3114558A1

    公开(公告)日：2017-01-11

    申请号：EP15711961.1

    申请日：2015-03-05

    申请人： Oracle International Corporation

    发明人： BROOKS, Jeffrey, S. ,  OLSON, Christopher, H. ,  MOGHADAM, Hesam, Fathi ,  EBERGEN, Josephus, C.

    IPC分类号： G06F7/483 ,  G06F7/491

    CPC分类号： G06F7/483 ,  G06F5/00 ,  G06F7/491 ,  G06F2207/3816 ,  G06F2207/483 ,  G06F2207/4912

    摘要： Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

    摘要翻译： 公开了一种用于对机器独立数字格式执行算术运算的处理器的实施例。 处理器可以包括浮点单元和数字单元。 数字格式可以包括符号/指数块，长度块和多个尾数位数。 数字单元可以被配置为通过转换每个操作数的每个尾数的数字格式来执行对两个操作数的操作，以使用转换的尾数来执行操作，然后将该操作结果的每个尾数转换回 转成原来的数字格式。

    Multiplying fixed-point binary numbers with variable number of fractional bits
    9.
    发明公开
    Multiplying fixed-point binary numbers with variable number of fractional bits 审中-公开
    MultiplizierungbinärerFestkommazahlen mit einerwählbahrenAnzahl von Fraktionalbits

    公开(公告)号：EP2857959A1

    公开(公告)日：2015-04-08

    申请号：EP14187342.2

    申请日：2014-10-01

    申请人： Rockwell Automation Technologies, Inc.

    发明人： Radtke, Christopher K.

    IPC分类号： G06F7/499 ,  G06F7/523

    CPC分类号： G06F17/10 ,  G06F7/49942 ,  G06F7/523 ,  G06F2207/3816

    摘要： Methods and systems for multiplying varying cast numbers are described herein. By using information related to the inputs to be multiplied, a single multiplier module may be used to multiply many different type cast numbers. These systems and methods may reduce hardware costs and complexity, reduce size of the circuitry, and/or reduce the complexity of the logic, among many other benefits. These systems and methods may be used with in industrial controllers in and industrial environment.

    摘要翻译： 本文描述了用于乘以变化铸件数量的方法和系统。 通过使用与要相乘的输入相关的信息，可以使用单个乘法器模块来乘以许多不同类型的转换数。 这些系统和方法可以降低硬件成本和复杂性，减小电路的尺寸和/或降低逻辑的复杂性等等。 这些系统和方法可以在工业控制器和工业环境中使用。

    Programmable logic device including multipliers and configurations thereof to reduce resource utilization
    10.
    发明公开
    Programmable logic device including multipliers and configurations thereof to reduce resource utilization 有权
    用乘法器和配置的可编程逻辑电路，以避免资源的磨损

    公开(公告)号：EP1294094A2

    公开(公告)日：2003-03-19

    申请号：EP02256303.5

    申请日：2002-09-11

    申请人： Altera Corporation

    发明人： Langhammer, Martin, c/o Altera Corporation ,  Hwang, Chiao Kai, c/o Altera Corporation ,  Starr, Gregory, c/o Altera Corporation

    IPC分类号： H03K17/00

    CPC分类号： H03K19/17744 ,  G06F7/523 ,  G06F2207/3816 ,  H03K19/17728 ,  H03K19/17732

    摘要： In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

    摘要翻译： 在具有专用器电路的可编程逻辑器件，一些扫描链寄存器的通常用于测试位于乘法器的相邻输入寄存器装置。 这些扫描链寄存器相与的输入寄存器，可与1和0的模板下载。 这允许，E. G.，如果装载有零点和剩余位的至少显著位被装入那些子集乘法。 乘法器优选地布置在与其它组分，色块：如加法器，确实允许它们被配置为有限脉冲响应（FIR）滤波器。 在寻求配置中，扫描链寄存器可以用来加载滤波器系数避免使用的设备的稀缺的逻辑和路由资源。