公开(公告)号：EP0117733A3

公开(公告)日：1985-11-27

申请号：EP84301195

申请日：1984-02-24

申请人： AMERICAN TELEPHONE AND TELEGRAPH COMPANY

发明人： Austin, Stewart Siegmund ,  Baldini III, Joseph John ,  Jakubson, Joel Eban ,  Ryan, Clarke Sylvester

IPC分类号： H04L07/04

CPC分类号： H04L1/0057 ,  H04L7/048

摘要： Circuitry for detecting errors in a digital bit stream comprising a succession of data blocks and wherein each block incorporates a parity check (P). At an error monitoring location (e.g. 100), a bistable device (e.g. 103) toggles in response to either a logical «1» or «0» in the bit stream. The output of the bistable device is sampled at a submultiple of the bit rate and compared with a predetermined criterion to detect bit errors.