WIDEBAND DIFFERENTIAL VOLTAGE-TO-CURRENT CONVERTERS
    2.
    发明公开
    WIDEBAND DIFFERENTIAL VOLTAGE-TO-CURRENT CONVERTERS 失效
    宽带VOLT AMP差分转换。

    公开(公告)号:EP0528940A1

    公开(公告)日:1993-03-03

    申请号:EP91909806.0

    申请日:1991-05-13

    Inventor: GILBERT, Barrie

    CPC classification number: H03F3/45071 H03F1/3211

    Abstract: Convertisseurs tension-courant (VI) du type à entrée et sortie différentielles destinés à être fabriqués sous forme de circuit intégré sur une seule puce monolithique. Le circuit comporte une première paire de résistances (RB) connectées entre les première et deuxième bornes d'entrée, dont leur noeud commun étant connecté aux bases de deux transistors de sortie NPN (Q1, Q2) qui fournissent des courants de sortie différentiels (IC1, IC2) à partir de leurs collecteurs. Les émetteurs de ces transistors sont connectés respectivement par l'intermédiaire de résistances correspondantes (RE/2), aux bornes d'entrée. Un condensateur (CB) est connecté entre les bases communes et la référence (terre)s pour établir une constante de temps appropriée afin d'arriver à un degré de complémentarité élevé. Ces particularités permettent d'éliminer essentiellement le courant de polarisation d'entrée et de réduire les distorsions paire et impaire du signal de sortie.

    AMPLIFIER HAVING LINEAR-IN-DB GAIN CONTROL
    3.
    发明公开
    AMPLIFIER HAVING LINEAR-IN-DB GAIN CONTROL 失效
    使用DB-线性增益控制放大器

    公开(公告)号:EP0867067A1

    公开(公告)日:1998-09-30

    申请号:EP96942946.0

    申请日:1996-12-12

    IPC: H03G7

    CPC classification number: H03G7/06

    Abstract: A variable gain amplifier (20) uses a differential attenuator (22) to provide a floating, high-impedance differential input to which a differential input signal is applied. The differential attenuator is comprised of (N-1) attenuator stages, with each stage forming a pair of attenuator taps for providing an attenuated version of the differential input signal. Each pair of taps is coupled to the differential inputs of a respective gm stage. The differential outputs of the gm stages are coupled to the differential inputs of a high open-loop gain main amplifier (28). The transconductance of each gm stage is controlled by an interpolator (26) which provides a bias current to each of the gm stages in a sequential manner as a gain control voltage is swept from its minimum to its maximum values. A gain response is produced that is linear-in-dB relative to the gain control voltage.

    LINEAR-IN-DECIBEL VARIABLE GAIN AMPLIFIER
    4.
    发明公开
    LINEAR-IN-DECIBEL VARIABLE GAIN AMPLIFIER 失效
    可变增益放大器和线性分贝

    公开(公告)号:EP0776548A1

    公开(公告)日:1997-06-04

    申请号:EP96923273.0

    申请日:1996-06-06

    Inventor: GILBERT, Barrie

    CPC classification number: H03G7/06 H03G7/001

    Abstract: A gain control circuit (22) provides linear-in-decibel gain control for an RF signal variable gain amplifier (12). The gain control circuit (22) utilizes the transconductance characteristics of bipolar transistors to generate a logarithmic relationship betweena gain control current (IG) and an amplifier bias current (IC). The gain control circuit (22) comprises essentially a current mirror having two transistors (Q1, Q2) with a resistor (R1) coupled between the associated base terminals of the two transistors (Q1, Q2). A third transistor (Q3) and a resistor (R2) are also provided to absorb the gain control current (IG). The gain control current (IG) is applied to a base of a first one (Q1) of the two transistors and a voltage is thereby established across the resistor. This voltage subtracts from the base-emitter voltage of the second transistor (Q2) thereby producing a corresponding exponential reduction in the current through the second transistor (Q2). This current (IC) is provided to a gm stage (12), whose gain is linearly proportional to this current. Thus, a linear change in the gain control current (IG) produces an exponential change in the gainof the gm stage (12). Accordingly, a linear-in dB variable gain amplifier is achieved.

    INTERPOLATOR HAVING DUAL TRANSISTOR RANKS AND RATIOMETRIC CONTROL
    5.
    发明授权
    INTERPOLATOR HAVING DUAL TRANSISTOR RANKS AND RATIOMETRIC CONTROL 有权
    在两行插值ARRANGED晶体管和关系比例控制

    公开(公告)号:EP1249069B1

    公开(公告)日:2004-03-17

    申请号:EP00984366.5

    申请日:2000-12-14

    Inventor: GILBERT, Barrie

    CPC classification number: H03G1/0035 H03G1/0088 H03H11/24

    Abstract: An interpolator utilizes two ranks of transistors to generate a plurality of interpolator currents within the confines of a low power supply voltage. The first rank of transistors are underdriven, thereby generating a plurality of partially switched currents having shallow Gaussian-shaped functions. The partially switched currents are then spatially amplified by the second rank of transistors to reduce the overlap of the currents from adjacent transistors. The first rank of transistors are driven ratiometrically by the difference of two control currents, thereby eliminating errors caused by inaccurate resistors and current sources. A biasing op-amp senses the interpolator currents and servos the first rank of transistors, thereby regulating the interpolator currents to a value determined by a reference voltage which is temperature compensated. Thus, the biasing op-amp automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator. A current generator utilizes a current mirror scheme and current replication techniques to cancel transistor alpha effects, thereby generating precise ratiometric drive currents from a low power supply voltage.

    RMS-DC CONVERTER HAVING DETECTOR CELL WITH DYNAMICALLY ADJUSTABLE SCALING FACTOR
    6.
    发明公开
    RMS-DC CONVERTER HAVING DETECTOR CELL WITH DYNAMICALLY ADJUSTABLE SCALING FACTOR 有权
    与动态调节刻度表因素检测CELL有效值DC-DC转换器

    公开(公告)号:EP1259929A1

    公开(公告)日:2002-11-27

    申请号:EP01910622.8

    申请日:2001-02-14

    Inventor: GILBERT, Barrie

    CPC classification number: G06G7/20 G01R19/02

    Abstract: A high-frequency RMS-DC converter having extended dynamic range operates by dynamically at low cost by adjusting the scaling factor (denominator) of a detector cell such as a squaring cell. The output from the squaring cell is averaged to generate a final output signal which can be fed back to a scaling input for operation in a measurement mode, or used to drive a power amplifier in a controller mode. By implementing the squaring cell as a transconductance cell using a modified multi-tanh structure, the scaling factor can be adjusted by dynamically changing the tail current through the cell which, in the measurement mode, is achieved by connecting the averaged output back to the squaring cell. An exponentially responding amplifier can be used in the feedback loop to provide a linear-in-dB output characteristic.

    DIFFERENTIAL AMPLIFIER WITH GAIN COMPENSATION
    8.
    发明授权
    DIFFERENTIAL AMPLIFIER WITH GAIN COMPENSATION 失效
    与Win补偿差分放大器。

    公开(公告)号:EP0465575B1

    公开(公告)日:1994-06-08

    申请号:EP90905991.7

    申请日:1990-03-23

    Inventor: GILBERT, Barrie

    CPC classification number: H03F3/45479 H03F1/302 H03F2203/45508

    Abstract: A differential amplifier (12, 14) including circuit means (20, 20) for generating a tail current which is not only proportional to absolute temperature, but also is adjusted to compensate for the non-ideal transistor geometries and properties, including finite beta and non-zero, temperature-dependent intrinsic resistances, so as to result in an amplification ratio which is substantially independent of all component variations.

    INTERPOLATOR HAVING DUAL TRANSISTOR RANKS AND RATIOMETRIC CONTROL
    9.
    发明公开
    INTERPOLATOR HAVING DUAL TRANSISTOR RANKS AND RATIOMETRIC CONTROL 有权
    在两行插值ARRANGED晶体管和关系比例控制

    公开(公告)号:EP1249069A2

    公开(公告)日:2002-10-16

    申请号:EP00984366.5

    申请日:2000-12-14

    Inventor: GILBERT, Barrie

    CPC classification number: H03G1/0035 H03G1/0088 H03H11/24

    Abstract: An interpolator utilizes two ranks of transistors to generate a plurality of interpolator currents within the confines of a low power supply voltage. The first rank of transistors are underdriven, thereby generating a plurality of partially switched currents having shallow Gaussian-shaped functions. The partially switched currents are then spatially amplified by the second rank of transistors to reduce the overlap of the currents from adjacent transistors. The first rank of transistors are driven ratiometrically by the difference of two control currents, thereby eliminating errors caused by inaccurate resistors and current sources. A biasing op-amp senses the interpolator currents and servos the first rank of transistors, thereby regulating the interpolator currents to a value determined by a reference voltage which is temperature compensated. Thus, the biasing op-amp automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator. A current generator utilizes a current mirror scheme and current replication techniques to cancel transistor alpha effects, thereby generating precise ratiometric drive currents from a low power supply voltage.

    RMS-DC CONVERTER HAVING GAIN STAGES WITH VARIABLE WEIGHTING COEFFICIENTS
    10.
    发明公开
    RMS-DC CONVERTER HAVING GAIN STAGES WITH VARIABLE WEIGHTING COEFFICIENTS 有权
    增益RMS DC转换器的可变加权系数STAGES

    公开(公告)号:EP1242828A2

    公开(公告)日:2002-09-25

    申请号:EP00988394.3

    申请日:2000-12-27

    Inventor: GILBERT, Barrie

    CPC classification number: H03G1/0088 G01R19/02 G05F3/222 G05F3/265

    Abstract: An RMS-DC converter generates a series of progressively amplified signal pairs which are then multiplied and weighted in such a way as to cancel uncorrelated noise while still providing true square-law response. The converter includes two series of gain stages for generating the amplified signal pairs, and a series of four-quadrant multipliers for multiplying and weighting the amplified signal pairs in response to series of weighting signals. The outputs from the multipliers are summed and averaged, and a final output signal is generated by integrating the difference between the averaged signal and a reference signal. To preserve the square-law response over a wide range of input voltages, the system is servoed by feeding the final output signal back to an interpolator which generates the weighting signals as a series of continuously interpolated, overlapping, Gaussian-shaped current pulses having a centroid that moves along the length of the interpolator as the final output signal varies. An embodiment can also be implemented with a single series of gain stages that generate a series of amplified signals which are squared, weighted, and averaged.

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