摘要:
A QAM demodulator is disclosed, which comprises two direct digital synthesizer circuits, for the provision of carrier synchronisation. The first DDS is located upstream of the receivers root-raised-cosine filter, and ensures frequency synchronisation, whilst the second DDS is downstream of the filter and ensures phase synchronisation.
摘要:
A QAM demodulator (99) having a first automatic gain control circuit (10) which outputs a first signal (94) that is a function of the received signal, the first signal being used to control the gain of an amplifier which supplies the input of an A/D converter (25), and a second automatic gain controller (20) which outputs a second signal derived from the QAM circuit after filtering, the second signal controlling the gain of a digital multiplier (210) which produces a signal which feeds into an equalizer (45) by way of a receive filter (40). The dual automatic gain control circuits (10, 20), situated before and after the receive filters (40), allow for better resistance to non-linearity caused by signals in adjacent channels. Additionally, the dual automatic gain control circuits allow for the amplification level of the signal to be limited before the demodulator to eliminate signal distortion and to be set to the correct level internally with digital gain. Also, there is no saturation of the A/D converter (25) since there is no QAM feedback to analog circuits. This architecture is particularly efficient in a variable rate transmission scheme.
摘要:
A timing recovery circuit (35) in a QAM demodulator which uses a symbol rate continously adaptive interpolation filter. The method of interpolation used in the present invention is defined as a function of time per interpolation inverval, rather than as a function of time per sampling interval as is commonly implemented in the prior art. This allows the interpolation filtering to be totally independent of the symbol rate in terms of complexity and performance and provides a better rejection of adjacent channels, since the interpolator rejects most of the signal outside the bandwidth of the received channel.
摘要:
A QAM demodulator (99) having a first automatic gain control circuit (10) which outputs a first signal (94) that is a function of the received signal, the first signal being used to control the gain of an amplifier which supplies the input of an A/D converter (25), and a second automatic gain controller (20) which outputs a second signal derived from the QAM circuit after filtering, the second signal controlling the gain of a digital multiplier (210) which produces a signal which feeds into an equalizer (45) by way of a receive filter (40). The dual automatic gain control circuits (10, 20), situated before and after the receive filters (40), allow for better resistance to non-linearity caused by signals in adjacent channels. Additionally, the dual automatic gain control circuits allow for the amplification level of the signal to be limited before the demodulator to eliminate signal distortion and to be set to the correct level internally with digital gain. Also, there is no saturation of the A/D converter (25) since there is no QAM feedback to analog circuits. This architecture is particularly efficient in a variable rate transmission scheme.
摘要:
A QAM demodulator having a carrier recovery circuit (50) that includes a phase estimation circuit (506) and an additive noise estimation circuit (507) which produces an estimation of the residual phase noise (518) and additive noise (519) viewed by the QAM demodulator. The phase noise estimation (518) is based on the least mean square error (512) between the QAM symbol (509) decided by a symbol decision circuit (508) and the received QAM symbol (504). The additive noise estimation is based on the same error as in the phase noise estimation (518), except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation (519) is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.
摘要:
A quadrature amplitude modulation type demodulator having a dual bit error rate estimator unit (70) that allows for high bit error rate measurements. The dual bit error rate estimator circuit (70) uses information pertaining to the number of corrected bytes from a forward error correction decoder (60) and the count of recognizable patterns of the frame over a sufficiently large number of frames. The two pieces of information can be compared at the bit error rate levels, where both the pattern recognition counter (62) and the FEC decoder (60) are able to output valid data. A comparison (710) between the two pieces of information provides a way to detect the type of noise which occurs on the network and makes it easier to correct problems in signal transmission.
摘要:
A QAM demodulator having a carrier recovery circuit (50) that includes a phase estimation circuit (506) and an additive noise estimation circuit (507) which produces an estimation of the residual phase noise (518) and additive noise (519) viewed by the QAM demodulator. The phase noise estimation (518) is based on the least mean square error (512) between the QAM symbol (509) decided by a symbol decision circuit (508) and the received QAM symbol (504). The additive noise estimation is based on the same error as in the phase noise estimation (518), except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation (519) is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.