公开(公告)号：EP3370235A2

公开(公告)日：2018-09-05

申请号：EP18159659.4

申请日：2018-03-02

申请人： AU Optronics Corporation

发明人： WANG, Chun-Min ,  WEI, Lin-Chieh

IPC分类号： G11C19/28 ,  G09G3/36 ,  G09G3/3266

CPC分类号： G09G3/3688 ,  G09G3/36 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2310/0286 ,  G11C19/28

摘要： A display panel (100) includes multiple gate lines (G1-G10) and a gate driver (120). The gate driver includes multiple shift registers (SR1-SR10, 200). Each of the shift registers includes a pull-up circuit (210), a driving circuit (220), and a pull-down circuit (230). The pull-up circuit charges a first node (NQ) in the shift register. The driving circuit is coupled to the first node, and outputs, according to a voltage signal of the first node, a driving pulse signal (G[n]) to a corresponding gate line. The pull-down circuit is coupled to the driving circuit, and discharges one of the gate lines according to the voltage signal of the first node. The shift register includes a first shift register (SRI) provided on a first side and a second shift register (SR2) provided on a second side. The pull-down circuit in the first shift register discharges a gate line corresponding to the second shift register according to the voltage signal of the first node.

公开(公告)号：EP3370235A3

公开(公告)日：2018-11-21

申请号：EP18159659.4

申请日：2018-03-02

申请人： AU Optronics Corporation

发明人： WANG, Chun-Min ,  WEI, Lin-Chieh

IPC分类号： G11C19/28 ,  G09G3/36 ,  G09G3/3266

CPC分类号： G09G3/3688 ,  G09G3/36 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2310/0286 ,  G11C19/28

摘要： A display panel (100) includes multiple gate lines (G1-G10) and a gate driver (120). The gate driver includes multiple shift registers (SR1-SR10, 200). Each of the shift registers includes a pull-up circuit (210), a driving circuit (220), and a pull-down circuit (230). The pull-up circuit charges a first node (NQ) in the shift register. The driving circuit is coupled to the first node, and outputs, according to a voltage signal of the first node, a driving pulse signal (G[n]) to a corresponding gate line. The pull-down circuit is coupled to the driving circuit, and discharges one of the gate lines according to the voltage signal of the first node. The shift register includes a first shift register (SRI) provided on a first side and a second shift register (SR2) provided on a second side. The pull-down circuit in the first shift register discharges a gate line corresponding to the second shift register according to the voltage signal of the first node.