公开(公告)号：EP4085329A1

公开(公告)日：2022-11-09

申请号：EP20908865.7

申请日：2020-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： BRANDL, Kevin M. ,  DAVANAM, Naveen ,  HOUSTY, Oswin E.

IPC: G06F9/4401 ,  G06F15/78 ,  G06F13/16 ,  G11C11/406

公开(公告)号：EP2443556B1

公开(公告)日：2014-02-19

申请号：EP10726762.7

申请日：2010-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： HOUSTY, Oswin E. ,  BAUTISTA, Harold H.

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1684 ,  G06F13/1689 ,  G06F13/4234

公开(公告)号：EP2443556A1

公开(公告)日：2012-04-25

申请号：EP10726762.7

申请日：2010-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： HOUSTY, Oswin E. ,  BAUTISTA, Harold H.

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1684 ,  G06F13/1689 ,  G06F13/4234

Abstract: In order to reduce training time and therefore boot time in computer systems, multiple memory channels are trained simultaneously. A training synchronizer receives training data and parameters for multiple memory channel controllers and includes a plurality of communication interfaces that simultaneously communicate over the communication interfaces with the memory channel controllers. The memory channel controllers are responsive to the training synchronizer to simultaneously train a plurality of memory channels coupled to respective ones of the memory channel controllers.