利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.009 秒)

    PRIMITIVE SHADER
    1.
    发明公开
    PRIMITIVE SHADER 有权
    原色遮阳板

    公开(公告)号：EP3300028A1

    公开(公告)日：2018-03-28

    申请号：EP17155075.9

    申请日：2017-02-07

    申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    发明人： NIJASURE, Mangesh ,  RAMSEY, Randy ,  MARTIN, Todd ,  MANTOR, Michael ,  LEFEBVRE, Laurent

    IPC分类号： G06T15/00

    CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/40 ,  G06T2200/04

    摘要： Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.

    摘要翻译： 公开了图形处理流水线的改进。 更具体地说，如果启用了细分，则新的基本着色器阶段执行顶点着色器阶段或域着色器阶段的任务，启用几何着色器，以及固定功能基元汇编器。 原始着色器阶段由用户提供的顶点或域着色器代码，几何着色器代码和执行原始汇编器功能的代码的驱动程序编译。 将固定功能原语汇编程序的任务移动到在可编程硬件中执行的原始着色器中，可以提供很多好处，例如移除固定功能交叉开关，去除在通用计算模式下不可用的专用参数和位置缓冲区等优点。

    COMBINED WORLD-SPACE PIPELINE SHADER STAGES
    4.
    发明公开
    COMBINED WORLD-SPACE PIPELINE SHADER STAGES 有权
    结合了世界各地的管道油漆装配阶段

    公开(公告)号：EP3300027A1

    公开(公告)日：2018-03-28

    申请号：EP17150441.8

    申请日：2017-01-05

    申请人： Advanced Micro Devices, Inc.

    发明人： NIJASURE, Mangesh ,  RAMSEY, Randy ,  MARTIN, Todd

    IPC分类号： G06T15/00

    CPC分类号： G06T15/80 ,  G06T15/005

    摘要： Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.

    摘要翻译： 披露了对图形处理管线的改进。 更具体地说，组合了执行顶点变换的顶点着色器阶段以及船体或几何着色器阶段。 如果曲面细分被禁用且几何着色被启用，则图形处理管线包括组合的顶点和图形着色器阶段。 如果启用镶嵌，则图形处理管线包括组合的顶点和外壳着色器阶段。 如果曲面细分和几何着色都被禁用，则图形处理管线不使用组合着色器阶段。 合并着色器阶段通过减少预定着色器程序和相关资源的执行实例数量来提高效率。

    COMBINED WORLD-SPACE PIPELINE SHADER STAGES
    7.
    发明授权
    COMBINED WORLD-SPACE PIPELINE SHADER STAGES 有权

    公开(公告)号：EP3300027B1

    公开(公告)日：2018-11-14

    申请号：EP17150441.8

    申请日：2017-01-05

    申请人： Advanced Micro Devices, Inc.

    发明人： NIJASURE, Mangesh ,  RAMSEY, Randy ,  MARTIN, Todd

    IPC分类号： G06T15/00

    CPC分类号： G06T15/80 ,  G06T15/005

    摘要： Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.