公开(公告)号：EP2240791A1

公开(公告)日：2010-10-20

申请号：EP09706465.3

申请日：2009-01-23

申请人： Alcatel-Lucent USA Inc.

发明人： CHAKRABORTY, Tapan, Jyoti ,  CHIANG, Chen-Huan ,  GOYAL, Suresh ,  PORTOLAN, Michele ,  VAN TREUREN, Bradford, Gene

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318558

摘要： The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy- enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

公开(公告)号：EP2232283A1

公开(公告)日：2010-09-29

申请号：EP08857895.0

申请日：2008-11-25

申请人： Alcatel-Lucent USA Inc.

发明人： CHAKRABORTY, Tapan, Jyoti ,  CHIANG, Chen-Huan ,  GOYAL, Suresh ,  PORTOLAN, Michele ,  VAN TREUREN, Bradford, Gene

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G06F17/50

CPC分类号： G01R31/318583 ,  G01R31/31704

摘要： The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system- on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system- on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.

公开(公告)号：EP2240790A1

公开(公告)日：2010-10-20

申请号：EP09705761.6

申请日：2009-01-21

申请人： Alcatel-Lucent USA Inc.

发明人： CHAKRABORTY, Tapan, Jyoti ,  CHIANG, Chen-Huan ,  GOYAL, Suresh ,  PORTOLAN, Michele ,  VAN TREUREN, Bradford, Gene

IPC分类号： G01R31/3185

CPC分类号： G01R31/318544 ,  G01R31/318536

摘要： The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level.

公开(公告)号：EP2232373A1

公开(公告)日：2010-09-29

申请号：EP08858340.6

申请日：2008-11-25

申请人： Alcatel-Lucent USA Inc.

发明人： CHAKRABORTY, Tapan, Jyoti ,  CHIANG, Chen-Huan ,  GOYAL, Suresh ,  PORTOLAN, Michele ,  VAN TREUREN, Bradford, Gene

IPC分类号： G06F11/26 ,  G01R31/3183

CPC分类号： G06F11/27 ,  G01R31/3177 ,  G01R31/318533 ,  G06F11/267

摘要： The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system- on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system- on-chip.