公开(公告)号：EP2624000A1

公开(公告)日：2013-08-07

申请号：EP10857801.4

申请日：2010-09-27

申请人： Fujitsu Limited

发明人： ITOZAWA, Shintaro ,  NISHIO, Masahiro ,  NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji ,  TAKAHASHI, Jin

IPC分类号： G01R31/28 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/318544 ,  G01R31/318541 ,  G01R31/318586

摘要： Object
An objective is to provide an integrated circuit capable of performing an operation check test for a combination circuit present in sections that are not connected by a scan chain.
Solution Means
An integrated circuit includes a first signal processing circuit in which a plurality of first combination circuits and a plurality of scan FFs (Flip Flop) are connected in an order of a scan FF, a first combination circuit, and a scan FF; a second signal processing circuit including a second combination circuit different from the first combination circuit; a first selection circuit configured to select data from a scan FF on an input side of one of the plurality of first combination circuits or data from an input terminal of the second signal processing circuit, and to output the selected data to the second combination circuit; and a second selection circuit configured to select data from another one of the plurality of first combination circuits different from the one of the plurality of first combination circuits or data from the second combination circuit, and to output the selected data to the scan FF on an output side of the another one of the plurality of first combination circuits.

摘要翻译： 目的是提供一种集成电路，其能够对未由扫描链连接的部分中存在的组合电路进行操作检查测试。 解决方案装置集成电路包括第一信号处理电路，其中多个第一组合电路和多个扫描FF（触发器）以扫描FF，第一组合电路和扫描FF的顺序连接; 第二信号处理电路，包括与第一组合电路不同的第二组合电路; 第一选择电路，被配置为从所述多个第一组合电路之一的输入侧的扫描FF或来自所述第二信号处理电路的输入端的数据中选择数据，并将所选择的数据输出到所述第二组合电路; 以及第二选择电路，被配置为从与所述多个第一组合电路不同的所述多个第一组合电路中的另一个组合电路或来自所述第二组合电路的数据中选择数据，并且将所选择的数据输出到所述扫描FF， 多个第一组合电路中的另一个的输出侧。

公开(公告)号：EP2316040A1

公开(公告)日：2011-05-04

申请号：EP09800722.2

申请日：2009-04-30

申请人： Synopsys, Inc.

发明人： KAPUR, Rohit ,  SAIKIA, Jyotirmoy ,  UPPULURI, Rajesh ,  NOTIYATH, Pramod ,  FERNANDES, Tammy ,  KULKARNI, Santosh ,  ANBALAN, Ashok

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： G01R31/318544 ,  G01R31/318583

摘要： Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.

公开(公告)号：EP2240790A1

公开(公告)日：2010-10-20

申请号：EP09705761.6

申请日：2009-01-21

申请人： Alcatel-Lucent USA Inc.

发明人： CHAKRABORTY, Tapan, Jyoti ,  CHIANG, Chen-Huan ,  GOYAL, Suresh ,  PORTOLAN, Michele ,  VAN TREUREN, Bradford, Gene

IPC分类号： G01R31/3185

CPC分类号： G01R31/318544 ,  G01R31/318536

摘要： The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level.

公开(公告)号：EP2053515B1

公开(公告)日：2010-09-08

申请号：EP07702184.8

申请日：2007-01-23

申请人： Huawei Technologies Co., Ltd.

发明人： HUA, Sizhen

IPC分类号： G06F11/24 ,  G01R31/3181 ,  G01R31/3185

CPC分类号： G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318572

公开(公告)号：EP2133705A1

公开(公告)日：2009-12-16

申请号：EP07740341.8

申请日：2007-03-29

申请人： Fujitsu Limited

发明人： OTAKE, Takashi

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318525

摘要： A faulty site identification apparatus (20) for identifying a faulty site in an integrated circuit, the apparatus includes a scan chain (12) that is constituted by coupling a plurality of sequential circuits (13), the scan chain outputs an output data array by shifting out setting data that is set to each of the plurality of sequential circuits (13); a setting section (22) that sets a predefined value to at least one sequential circuit (18) of the plurality of sequential circuits (13) as the setting data; and an identification section (24) that identifies a faulty site in the scan chain (12) on the basis of the output data array from the scan chain (12) and a location of the at least one sequential circuit (18) in the scan chain (12) . Thereby, any faulty site in the scan chain can be easily and quickly identified in the scan test.

摘要翻译： 一种用于识别集成电路中的故障位置的故障现场识别装置（20），该装置包括通过耦合多个顺序电路（13）构成的扫描链（12），扫描链通过 移位设定为多个顺序电路（13）中的每一个的设定数据; 将所述多个顺序电路（13）中的至少一个时序电路（18）的预定值设定为设定数据的设定部（22） 以及识别部分（24），其基于来自扫描链（12）的输出数据阵列和扫描中的至少一个顺序电路（18）的位置来识别扫描链（12）中的故障位置 链（12）。 因此，扫描链中的任何故障现场可以在扫描测试中轻松快速地识别。

公开(公告)号：EP1451599A1

公开(公告)日：2004-09-01

申请号：EP02789591.1

申请日：2002-11-12

申请人： Intellitech Corporation

发明人： RICCHETTI, Michael ,  CLARK, Christopher, J.

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318555

摘要： An embedded electronic sxstem built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and/or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

公开(公告)号：EP1306684A2

公开(公告)日：2003-05-02

申请号：EP02028090.5

申请日：1998-04-24

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Hosokawa, Toshinori ,  Ohta, Mitsuyasu

IPC分类号： G01R31/3181

CPC分类号： G01R31/318547 ,  G01R31/318392 ,  G01R31/318544 ,  G01R31/318586

摘要： Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs. Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop. and the structure of the integrated circuit is checked if it has an-fold line-up structure, and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs. For example, timeframe expansion on the basis of the state justification of load/hold FFs is carried out. From such timeframe expansion, FFs to replace with scan FFs are selected. This guarantees high fault efficiency in identifying FFs to replace with scan FFs. In generating test sequences for the post-fabrication testing of ICs, a buffer length for a buffer storing a test sequence is set and a test sequence for an integrated circuit is generated while sequentially compaction storing test sequences for respective faults in buffers with the set buffer length. This achieves a higher compaction rate than conventional technology.

摘要翻译： 针对设计在门级的集成电路选择用扫描FF替换的触发器（FF），以便集成电路具有n-fold阵列结构。 集成电路中的所有FF都被暂时选为FF，以替换为扫描FF。 将用扫描FF替换的每个FF被暂时选择为FF以用非扫描触发器替代。 并且如果它具有折叠阵列结构，则检查集成电路的结构，如果是，则将FF选择为FF以用非扫描触发器替代。 对于在门级设计的集成电路，选择用扫描触发器代替的触发器，以便集成电路具有n倍的阵列结构，而不将负载/保持FF识别为自环结构FF 。 此后，以扫描FF替换的FF被选择为便于对加载/保持FF进行测试。 例如，基于负载/保持FF的状态调整的时间帧扩展被执行。 从这种时间范围扩展中，选择FF来替换扫描FF。 这确保识别FF以更换扫描FF的故障效率很高。 在产生用于IC的制造后测试的测试序列中，设置存储测试序列的缓冲器的缓冲器长度，并且产生用于集成电路的测试序列，同时依次压缩存储具有设定缓冲器的缓冲器中各个故障的测试序列 长度。 这实现了比传统技术更高的压实率。

公开(公告)号：EP1015899A4

公开(公告)日：2002-11-13

申请号：EP98914261

申请日：1998-03-18

申请人： INTEL CORP

发明人： WU DAVID ,  PARVATHALA PRAVEEN ,  GOLLAKOTA NAGA

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318586

摘要： A method and apparatus for using weighted random patterns in a partial scan test. A computer generates deterministic patterns (304) on the partial scan design. Deterministic patterns that have the same number of capture clocks between adjacent scan loads are grouped together into pattern groups (308). A computer then determines a set of weights corresponding to each of the pattern groups (312). A tester then uses these weights as a filter to weighted random test patterns and applies these filtered weighted random test patterns along with the appropriate number of capture clock pulses to a device under test.

公开(公告)号：EP0367710A2

公开(公告)日：1990-05-09

申请号：EP89480167.9

申请日：1989-10-24

申请人： International Business Machines Corporation

发明人： Hsieh, Edward Po-Chiu ,  McMahon, Maurice Thomas ,  Schnurmann, Henri Daniel

IPC分类号： G06F11/22

CPC分类号： G06F11/261 ,  G01R31/318544 ,  G01R31/318566 ,  G06F11/2733

摘要： A method and circuitry for testing in situ the compo­nents mounted on a circuit board. First, a component is removed from the board. A testing circuit is then in­stalled in place of the removed component. The testing circuit allows test patterns to be applied to a selected component on the board from the board I/O pins. The selected component responses are collected by the testing circuit and applied to the board output pins. In this manner, individual components on the board can be tested in situ from pins on the board.

摘要翻译： 一种用于原位测试安装在电路板上的组件的方法和电路。 首先，组件从板上移除。 然后安装测试电路来代替去除的部件。 测试电路允许从板I / O引脚将测试图案应用于板上的选定组件。 所选择的组件响应由测试电路收集并应用于电路板输出引脚。 以这种方式，板上的各个部件可以从板上的引脚原位进行测试。

公开(公告)号：EP0295388A2

公开(公告)日：1988-12-21

申请号：EP88106203.8

申请日：1988-04-19

申请人： International Business Machines Corporation

发明人： Jacobs, Scott Laurence ,  McMahon, Maurice Thomas Jr. ,  Nihal, Perwaiz ,  Ozmat, Burhan ,  Schnurmann, Henri Daniel ,  Zingher, Arthur Richard

IPC分类号： G06F11/22 ,  G06F11/26

CPC分类号： G01R31/318544 ,  G01R31/318385 ,  G06F11/27

摘要： A selfcontained method and structure for partitioning, testing and diagnosing a multichip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multichip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

摘要翻译： 用于划分，检测和诊断的多芯片封装结构的自包含方法和结构。 该方法包括的电子抑制所有芯片在多芯片封装除了被测芯片或芯片，通过产生和应用随机模式下测试芯片或芯片下测试创建芯片或芯片的签名的步骤（通过向称为 检测中的元件）和相比较而获得的“好机”模拟签名的签名。 结构包括用于实现上述方法步骤。 具有内置冗余的自测试电路具有安装在所述半导体衬底的电路ECIPT半导体衬底和芯片的优选结构包括。 全部或自检电路，包括所需的多路转换器等的一部分，可以被并入到所述半导体衬底。 因此ECIPT电路可以被构建到下面的每个芯片的网站上的底物。 沿着芯片边界，而无需外部测试器或大型计算机，以及增强的诊断简单且廉价的测试分区的组合是由本发明制造的可能的。