公开(公告)号：EP1729198A2

公开(公告)日：2006-12-06

申请号：EP06009561.9

申请日：2006-05-09

申请人： Altera Corporation

发明人： Lim, Chooi Pei ,  Too, Joo Ming ,  Kok, Yew Fatt (Edwin) ,  Chua, Kar Keng

IPC分类号： G06F1/10

CPC分类号： H03K19/1774 ,  G06F1/10

摘要： Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

摘要翻译： 用于结构化ASIC器件的时钟分配电路包括确定性部分和可配置部分。 确定部分采用预定布置的导体段和缓冲器，用于将时钟信号分配到设备上的多个预定位置。 从每个预定位置，时钟分配电路的相关联的可配置部分将时钟信号分配到在从该预定位置服务的结构化ASIC的预定区域中需要该时钟信号的任何时钟利用电路。