公开(公告)号：EP4398115A2

公开(公告)日：2024-07-10

申请号：EP24167536.2

申请日：2022-08-23

申请人： Apple Inc.

发明人： HAMMARLUND, Per H. ,  ZIMET, Lior ,  KOLOR, Sergio ,  LAHAV, Sagi ,  VASH, James ,  GARG, Gaurav ,  KUZI, Tal ,  GONION, Jeffry E. ,  TUCKER, Charles E. ,  LEVY-RUBIN, Lital ,  DAVIDOV, Dany ,  FISHWICK, Steven ,  LESHEM, Nir ,  PILIP, Mark ,  WILLIAMS, III Gerard R. ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  TAMARI, Eran ,  TOTA, Sergio V. ,  REDSHAW, Jonathan M. ,  HUTSELL, Steven R. ,  FUKAMI, Shawn M. ,  GUNNA, Ramesh B.

IPC分类号： G06F13/10

CPC分类号： Y02D10/00 ,  G06F13/161 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/1668 ,  G06F15/7807 ,  G06F2212/104820130101 ,  G06F2212/102420130101 ,  G06F12/0824 ,  G06F12/0833 ,  G06F12/0813 ,  G06F2212/45520130101

摘要： A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.

公开(公告)号：EP4398114A2

公开(公告)日：2024-07-10

申请号：EP24165580.2

申请日：2022-08-23

申请人： Apple Inc.

发明人： HAMMARLUND, Per H. ,  ZIMET, Lior ,  KOLOR, Sergio ,  LAHAV, Sagi ,  VASH, James ,  GARG, Gaurav ,  KUZI, Tal ,  GONION, Jeffry E. ,  TUCKER, Charles E. ,  LEVY-RUBIN, Lital ,  DAVIDOV, Dany ,  FISHWICK, Steven ,  LESHEM, Nir ,  PILIP, Mark ,  WILLIAMS, Gerard R. III ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  TAMARI, Eran ,  TOTA, Sergio V. ,  REDSHAW, Jonathan M. ,  HUTSELL, Steven R. ,  FUKAMI, Shawn M. ,  GUNNA, Ramesch B.

IPC分类号： G06F13/10

CPC分类号： Y02D10/00 ,  G06F13/161 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/1668 ,  G06F15/7807 ,  G06F2212/104820130101 ,  G06F2212/102420130101 ,  G06F12/0824 ,  G06F12/0833 ,  G06F12/0813 ,  G06F2212/45520130101

摘要： A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.