公开(公告)号：EP4381388A1

公开(公告)日：2024-06-12

申请号：EP21801665.7

申请日：2021-10-14

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： ROOZBEH, Amir ,  PADALA, Chakri ,  FARSHIN, Alireza Farshin

IPC分类号： G06F9/50 ,  G06F12/084

CPC分类号： G06F9/5016 ,  G06F12/084 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/0813 ,  G06F2212/102420130101 ,  G06F2212/104820130101

公开(公告)号：EP4356252A1

公开(公告)日：2024-04-24

申请号：EP22754814.6

申请日：2022-07-19

申请人： International Business Machines Corporation

发明人： GUPTA, Lokesh, Mohan ,  ANDERSON, Kyler ,  ASH, Kevin ,  KALOS, Matthew ,  RINALDI, Brian, Anthony ,  PETERSON, Beth, Ann ,  BORLICK, Matthew

IPC分类号： G06F12/02

CPC分类号： G06F2212/21420130101 ,  G06F12/0895 ,  G06F2212/46220130101 ,  G06F12/0871 ,  G06F12/123 ,  G06F2212/50220130101 ,  G06F12/0868 ,  G06F2212/31220130101 ,  G06F2212/103220130101 ,  G06F2212/102420130101 ,  G06F2212/104820130101 ,  G06F11/00

公开(公告)号：EP4432105A1

公开(公告)日：2024-09-18

申请号：EP24163275.1

申请日：2024-03-13

申请人： Samsung Electronics Co., Ltd.

发明人： RIESEN, Rolf ,  TAUFERNER, Andrew ,  LOMBARD, David ,  JOSEPH, Douglas ,  DAYAL, Jai ,  LOO, James ,  WOLF, Matthew ,  WISNIEWSKI, Robert

IPC分类号： G06F12/1072 ,  G06F12/109 ,  G06F9/54

CPC分类号： G06F12/1072 ,  G06F2212/65720130101 ,  G06F12/109 ,  G06F2212/65120130101 ,  G06F2212/65620130101 ,  G06F2212/15420130101 ,  G06F2212/104820130101 ,  G06F2212/105620130101 ,  G06F2212/100820130101 ,  G06F2212/25420130101 ,  G06F9/546

摘要： A computing node in a multi-node computing system includes a local memory, at least one processor, and an access library. The at least one processor runs an operating system that runs a distributed application in a virtual address space. The application includes a process that generates a first memory access request that includes a first virtual address. The access library is responsive to the first memory access request by: converting the first virtual address into a first physical address, accessing the local memory based on the first physical address including a first indication that the first memory access request is for the local memory, and accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node.

公开(公告)号：EP4398114A2

公开(公告)日：2024-07-10

申请号：EP24165580.2

申请日：2022-08-23

申请人： Apple Inc.

发明人： HAMMARLUND, Per H. ,  ZIMET, Lior ,  KOLOR, Sergio ,  LAHAV, Sagi ,  VASH, James ,  GARG, Gaurav ,  KUZI, Tal ,  GONION, Jeffry E. ,  TUCKER, Charles E. ,  LEVY-RUBIN, Lital ,  DAVIDOV, Dany ,  FISHWICK, Steven ,  LESHEM, Nir ,  PILIP, Mark ,  WILLIAMS, Gerard R. III ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  TAMARI, Eran ,  TOTA, Sergio V. ,  REDSHAW, Jonathan M. ,  HUTSELL, Steven R. ,  FUKAMI, Shawn M. ,  GUNNA, Ramesch B.

IPC分类号： G06F13/10

CPC分类号： Y02D10/00 ,  G06F13/161 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/1668 ,  G06F15/7807 ,  G06F2212/104820130101 ,  G06F2212/102420130101 ,  G06F12/0824 ,  G06F12/0833 ,  G06F12/0813 ,  G06F2212/45520130101

摘要： A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. An interconnect fabric included in the system includes at least two networks having heterogeneous interconnect topologies. The at least two networks include a coherent network interconnecting the processor cores and the plurality of memory controllers.

公开(公告)号：EP4443298A1

公开(公告)日：2024-10-09

申请号：EP23204125.1

申请日：2023-10-17

申请人： INTEL Corporation

发明人： KUMAR, Karthik ,  GUIM BERNAT, Francesc ,  KRITHIVAS, Ramamurthy

IPC分类号： G06F11/10

CPC分类号： G06F12/0284 ,  G06F2212/40320130101 ,  G06F2212/103220130101 ,  G06F2212/50220130101 ,  G06F2212/105620130101 ,  G06F2212/105220130101 ,  G06F2212/104820130101 ,  G06F12/1408 ,  G06F11/1048

摘要： Techniques for adaptive memory metadata allocation. A processor may determine a first memory region of a plurality of memory regions in a memory pool coupled to the processor via an interface. The processor may modify a metadata of the first memory region from a first configuration to a second configuration, where the first configuration is associated with a first number of error correction code (ECC) bits and the second configuration is associated with a second number of ECC bits.

公开(公告)号：EP3920034B1

公开(公告)日：2024-06-12

申请号：EP21175017.9

申请日：2021-05-20

IPC分类号： G06F12/02 ,  G06F12/0815 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897 ,  G06F15/173 ,  G06F12/1072 ,  G06F12/0888

CPC分类号： G06F12/0815 ,  G06F12/0897 ,  G06F12/0871 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0284 ,  G06F2212/104820130101 ,  G06F2212/15420130101 ,  G06F2212/60120130101 ,  G06F2212/21720130101 ,  G06F2212/28320130101 ,  G06F15/17331 ,  Y02D10/00

公开(公告)号：EP3948549B1

公开(公告)日：2024-05-08

申请号：EP19922898.2

申请日：2019-03-29

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/0817 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/0804

CPC分类号： G06F2212/104820130101 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0868 ,  G06F2212/46620130101 ,  G06F2212/28320130101 ,  G06F12/0897 ,  G06F2212/102420130101

公开(公告)号：EP4425341A2

公开(公告)日：2024-09-04

申请号：EP24188876.7

申请日：2015-09-15

申请人： Kove IP, LLC

发明人： STABRAWA, Timothy A. ,  CORNELIUS, Zachary A. ,  OVERTON, John ,  POLING, Andrew S. ,  TAYLOR, Jesse I.

IPC分类号： G06F12/08

CPC分类号： H04L67/1097 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/104820130101 ,  Y02D10/00

摘要： A memory appliance may be provided comprising a processor, a communication interface, a memory, and a region access unit. The memory may be configured in an address space addressable by the processor. The communication interface may be configured to provide the client access to the region of the memory via client-side memory access before initialization of all of the region. A method to create a virtual copy of memory accessible by client-side memory access is also provided. A system may be provided that memory maps at least a portion of a file to a memory region, wherein a virtual address addressable is generated, and the at least a portion of file is accessible through the memory region at the virtual address. The virtual address may be registered with the communication interface, where registration of the virtual address provides client-side memory access to the memory region.

公开(公告)号：EP3799396B1

公开(公告)日：2024-07-17

申请号：EP20207722.8

申请日：2015-09-15

IPC分类号： H04L67/1097 ,  G06F12/10 ,  G06F12/08

CPC分类号： H04L67/1097 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/104820130101 ,  Y02D10/00

公开(公告)号：EP4345635A3

公开(公告)日：2024-05-29

申请号：EP24157211.4

申请日：2019-06-18

申请人： FLC Technology Group Inc.

发明人： SUTARDJA, Sehat

IPC分类号： G06F12/0804 ,  G06F12/02 ,  G06F12/0862 ,  G06F3/06 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/1027 ,  G06F12/123

CPC分类号： G06F12/0811 ,  G06F12/084 ,  G06F12/0871 ,  G06F2212/46320130101 ,  G06F2212/31120130101 ,  G06F2212/21420130101 ,  G06F2212/104120130101 ,  G06F2212/102420130101 ,  G06F2212/104820130101 ,  G06F12/0888 ,  G06F12/123 ,  G06F12/1027 ,  G06F2212/720120130101 ,  G06F2212/68420130101 ,  G06F12/0851 ,  Y02D10/00 ,  G06F12/0897

摘要： A data storage and access system for use with a processor having a final level cache (FLC) cache system, configured to function as main memory and receive a data request from the processor, that has processor cache. The FLC system comprises a first FLC module having a first FLC controller and first memory, where the first FLC module is configured to receive the data request from the processor. The FLC system additionally comprises a second FLC module having a second FLC controller and second memory. The second FLC module is configured to receive, responsive to the first FLC module not having the data requested by the processor, the data request from the first FLC module and forward the data request to a storage drive or a third FLC module to retrieve the data identified by the data request.