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公开(公告)号:EP3872561A1
公开(公告)日:2021-09-01
申请号:EP19856413.0
申请日:2019-08-27
发明人: WANG, Xiaoyuan , WANG, Wu , FANG, Yan , BI, Ruilin , BAI, Yajie , GAO, Yujie , LEE, Seungmin
IPC分类号: G02F1/1343 , G02F1/1362
摘要: An array substrate includes a base substrate; a data line and a common electrode line on the base substrate; and a first gate line and a second gate line on the base substrate, both the first gate line and the second gate line cross both the data line and the common electrode line to define a sub-pixel. The sub-pixel includes: a pixel electrode; a common electrode; and an insulating layer between the pixel electrode and the common electrode. The common electrode includes a plurality of slits, and the slits extend in the same direction as the data line. The slits include a first slit close to the data line, the pixel electrode includes a first side surface close to the data line, and an orthographic projection of the first side surface on the base substrate is located within an orthographic projection of the first slit on the base substrate.
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公开(公告)号:EP4312265A3
公开(公告)日:2024-04-17
申请号:EP23215698.4
申请日:2019-12-18
发明人: WANG, Xiaoyuan , WANG, Wu , FANG, Yan , WU, Shengxue
IPC分类号: G02F1/1362 , H01L23/485 , H01L23/528
CPC分类号: H01L23/528 , H01L23/485 , H01L27/124 , H01L27/1248 , G02F1/134372 , G02F1/136227
摘要: Disclosed are an array substrate and a method for preparing same, and a display panel. The array substrate comprises: a base (10); a pixel electrode (50) and a thin-film transistor which are provided on the base (10); a passivation layer (16) covering the thin-film transistor and the pixel electrode (50), wherein an adapting via hole (K1, K2), which simultaneously exposes the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin-film transistor, is provided in the passivation layer (16); and a connection electrode (60) which is provided on the passivation layer (16) and is at the adapting via hole (K1, K2), wherein the connection electrode (60) is simultaneously connected, through the adapting via hole (K1, K2), to the pixel electrode (50) and the drain electrode (15) or the source electrode (14). Realizing connection between the drain electrode (15) or the source electrode (14) and the pixel electrode (50) by providing the adapting via hole (K1, K2) effectively reduces the number of via holes, increases an aperture ratio of the display panel, improves product quality, and improves the yield.
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公开(公告)号:EP3913427A1
公开(公告)日:2021-11-24
申请号:EP19910539.6
申请日:2019-12-18
发明人: WANG, Xiaoyuan , WANG, Wu , FANG, Yan , WU, Shengxue
IPC分类号: G02F1/1362 , H01L23/485 , H01L23/528
摘要: Disclosed are an array substrate and a method for preparing same, and a display panel. The array substrate comprises: a base (10); a pixel electrode (50) and a thin-film transistor which are provided on the base (10); a passivation layer (16) covering the thin-film transistor and the pixel electrode (50), wherein an adapting via hole (K1, K2), which simultaneously exposes the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin-film transistor, is provided in the passivation layer (16); and a connection electrode (60) which is provided on the passivation layer (16) and is at the adapting via hole (K1, K2), wherein the connection electrode (60) is simultaneously connected, through the adapting via hole (K1, K2), to the pixel electrode (50) and the drain electrode (15) or the source electrode (14). Realizing connection between the drain electrode (15) or the source electrode (14) and the pixel electrode (50) by providing the adapting via hole (K1, K2) effectively reduces the number of via holes, increases an aperture ratio of the display panel, improves product quality, and improves the yield.
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公开(公告)号:EP4312265A2
公开(公告)日:2024-01-31
申请号:EP23215698.4
申请日:2019-12-18
发明人: WANG, Xiaoyuan , WANG, Wu , FANG, Yan , WU, Shengxue
IPC分类号: H01L23/528
摘要: Disclosed are an array substrate and a method for preparing same, and a display panel. The array substrate comprises: a base (10); a pixel electrode (50) and a thin-film transistor which are provided on the base (10); a passivation layer (16) covering the thin-film transistor and the pixel electrode (50), wherein an adapting via hole (K1, K2), which simultaneously exposes the pixel electrode (50) and a drain electrode (15) or a source electrode (14) of the thin-film transistor, is provided in the passivation layer (16); and a connection electrode (60) which is provided on the passivation layer (16) and is at the adapting via hole (K1, K2), wherein the connection electrode (60) is simultaneously connected, through the adapting via hole (K1, K2), to the pixel electrode (50) and the drain electrode (15) or the source electrode (14). Realizing connection between the drain electrode (15) or the source electrode (14) and the pixel electrode (50) by providing the adapting via hole (K1, K2) effectively reduces the number of via holes, increases an aperture ratio of the display panel, improves product quality, and improves the yield.
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公开(公告)号:EP3871041A1
公开(公告)日:2021-09-01
申请号:EP19853278.0
申请日:2019-03-25
发明人: WANG, Xiaoyuan , WANG, Wu , FANG, Yan , BAI, Yajie , BI, Ruilin
IPC分类号: G02F1/1343
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公开(公告)号:EP3686665A1
公开(公告)日:2020-07-29
申请号:EP18857955.1
申请日:2018-09-14
发明人: WANG, Xiaoyuan , YANG, Ni , FANG, Yan , XU, Hengyi , LI, Yunze
IPC分类号: G02F1/1343
摘要: A pixel structure, an array substrate and a display device, relating to the technical field of display. The pixel structure comprises: a plate electrode (1), an interlayer insulating layer (5) and a strip electrode (20) which are configured to be sequentially arranged on a substrate (10); the strip electrode (20) comprises a first strip electrode (21), a second strip electrode (22) and a third strip electrode (23); the first strip electrode (21) and the plate electrode (1) are oppositely arranged, such that the orthographic projection of the first strip electrode (21) on the substrate (10) at least partly overlaps with the orthographic projection of the plate electrode (1) on the substrate (10); during display, the first strip electrode (21) and the plate electrode (1) are configured to be applied with different voltages.
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