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公开(公告)号：EP3678124A1
公开(公告)日：2020-07-08
申请号：EP18800027.7
申请日：2018-04-27
发明人： XU, Zhuo , BAI, Yajie , WU, Hailong , ZHOU, Yan , LIANG, Peng , RAN, Min , ZHU, Haipeng
IPC分类号： G09G3/36
摘要： A shift register unit, a driving device, a display device and a driving method are disclosed. The shift register unit (10) includes a first circuit unit (100) and a second circuit unit (200); the first circuit unit (100) includes an input terminal (INPUT), a reset terminal (RESET), a clock signal terminal (CLK), a first voltage terminal (VGH), a second voltage terminal (VGL) and a first output terminal (OUTPUT), and is configured to output a first output signal of the shift register unit (10) from the first output terminal (OUTPUT); the second circuit unit includes a third voltage terminal (VGH2), a fourth voltage terminal (VGL2) and a second output terminal (OUTPUT2), and is configured to output a second output signal of the shift register unit (10) from the second output terminal (OUTPUT2), at least under the control of the first output signal; and the second output signal and the first output signal are mutually phase-inverted signals.
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2.发明公开
公开(公告)号：EP3770897A1
公开(公告)日：2021-01-27
申请号：EP19771375.3
申请日：2019-03-22
发明人： XU, Zhuo , ZHANG, Yuanbo , BAI, Yajie , ZHU, Haipeng , ZHOU, Yan , WU, Hailong , KIM, Heecheol , RAN, Min
IPC分类号： G09G3/36
摘要： A shift register circuit, comprising a first circuit 10, M second circuits 20, and N third circuits 30. A first signal output end OUTPUT1 of the first circuit 10 is connected to a second signal input end INPUT2 of each second circuit 20; each second signal output end OUTPUT2 is connected to third signal input ends INPUT3 of the N/M third circuits 30, and different second signal output ends OUTPUT2 are connected to different third signal input ends INPUT3; and different second circuits 20 are connected to different control clock signal ends CLKm, and different third circuits 30 are connected to different output clock signal ends CLKn.
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