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公开(公告)号：EP0098494A2
公开(公告)日：1984-01-18
申请号：EP83106239.3
申请日：1983-06-27
IPC分类号： G06F13/00
摘要： Asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus (DAC BUS).
Microinstructions can be read out from working memory.
At least one of the processors, in addition to conventional bus interface registers for latching of data, address, commands to be forwarded to the working memory through the bus, is provided with an additional interface register (39), devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. It is further provided with a multiplexer (17) for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus.
A direct path (25) is established between the system common bus and an input set of the multiplexer.
The microinstruction transfer speed from working memory to the processor is enhanced by means of different timing for the data transfer through the bus and the microinstruction transfer through the bus. Whilst in case of data transfer a bus access cycle is started at the end of the processor cycle during which the relevant bus interface register are loaded, in the case of microinstruction read out from working memory, the additional interface register is loaded at the beginning of a processor cycle concurrently with the request of bus access cycle, so that the two, may overlap.摘要翻译： 异步总线多处理器系统，其中多个微程序处理器通过公共总线（DAC BUS）与工作存储器通信。 ... 微指令可以从工作记忆中读出。 ...除了传统的总线接口寄存器，用于锁存数据，地址，通过总线转发到工作存储器的命令之外，至少有一个处理器具有附加的接口寄存器（39），专用 将微指令的微指令地址的锁存从工作存储器中读出。 还设置有用于从微程序控制存储器或从系统公共总线选择性地加载微指令寄存器的多路复用器（17）。 在系统公共总线和多路复用器的输入集之间建立直接路径（25）。 ...从工作存储器到处理器的微指令传输速度通过总线的数据传输的不同时序和通过总线的微指令传输来增强。 在数据传输的情况下，在加载相关总线接口寄存器的处理器周期结束时开始总线访问周期，在从工作存储器读出微指令的情况下，附加接口寄存器在 处理器周期与总线访问周期的请求同时进行，以便两者可能重叠。
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