摘要:
A DFG (100) has inputs A and B linked by edges (140) and (150), respectively, to an operator NI illustrated at (125). DFG (100) has inputs C and D linked by edges (145) and (160), respectively, to an operator N2 illustrated at (130). Operators NI and N2 (125) and (130) are illustrated as addition operators but could any of a variety of types of operators. The bitwidths of edges (140, 145, 150 and 160) are equal to 8. The widths of operators N1 and N2 (125) and (130) are equal to 9. While an output edge (155) has a bitwidth of 9. Which corresponds to the operator N2 (130), that of an output corresponds to the output of operator N2 (130) that of an output edge (165) which corresponds to the output of operator N1 (125), is equal to 7 so the output of node N1 (125) is obtained by truncating a 9 bit result to 7 bits by the operator N1 (125).
摘要:
A Huffman algorithm is applied to revise the topology of a data flow graph. The result of the application of the algorithm is an increase in the sizes of at least some of the clusters through enhanced mergeability. The Huffman rebalancing of the topology may also result in the benefit of allowing further pruning of the bitwidths of data flow paths, which may further enhance mergeability.
摘要:
A practical definition for determining an upper bound on information content is provided and used to reduce the widths of operators and edges of data flow graphs (100). A top down procedure for systematically pruning data flow graph is described. The result is shown to enhance the mergeability of subgraphs (105 & 110) and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.
摘要:
A practical definition for determining a required precision is provided and used to reduce the widths of operators (225, 230) and edges of data flow graphs (200). A bottom-up procedure for systematically pruning data flow graphs is described. The result is shown to enhance the mergeability of subgraphs and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.