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    Fuzzy logic analog computer architecture
    2.
    发明公开
    Fuzzy logic analog computer architecture 失效
    Architektur eines analogen Fuzzy-Logik-Rechners

    公开(公告)号：EP0709790A1

    公开(公告)日：1996-05-01

    申请号：EP94830517.2

    申请日：1994-10-31

    申请人： CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

    发明人： Bruno,Dario ,  Giacalone,Biagio ,  Manaresi, Nicolò

    IPC分类号： G06G7/26 ,  G05F3/24

    CPC分类号： G05F3/24 ,  G06N7/043

    摘要： Analog processor (2) of antecedent parts of fuzzy logic inference rules and comprising a plurality of analog generators (3) of membership function (FA) each having an output (4) supplying a value corresponding to a degree of truth complemented to one (α') of logical assignments of the type (A is A') with the outputs (4) being connected together to form a common circuit node (7) and also connected to a current generator (9) and the processor (2) comprising also a voltage control device (5) inserted between a supply voltage pole (V D ) and a ground voltage reference (GND) and a one-way element (8) connected to the common circuit node (7) and the one-way element (8) having an output (10) producing an overall degree of truth (Ω) for the antecedent part of the fuzzy rule to be processed.

    摘要翻译： 模糊逻辑推理规则的先前部分的模拟处理器（2），包括多个隶属函数（FA）的模拟发生器（3），每个模拟发生器（3）具有输出（4），该输出（4）提供对应于一个（α （A）的逻辑分配，其中输出端（4）被连接在一起以形成公共电路节点（7）并且还连接到电流发生器（9），并且处理器（2）还包括 插入在电源电压极（VD）和接地电压基准（GND）之间的电压控制装置（5）和连接到公共电路节点（7）和单向元件（8）的单向元件（8） ）具有对待处理的模糊规则的先行部分产生总体真实度（OMEGA）的输出（10）。