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公开(公告)号：EP1032887A1
公开(公告)日：2000-09-06
申请号：EP98959468.4
申请日：1998-11-16
申请人： CRAY RESEARCH, INC.
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communications links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and include ports for receiving and sending messages, and lookup tables having a local router table having directions for routing between processor element nodes within a global partition, and a global router table having directions for routing between processor element nodes located in different global partitions. The directions from the local table are selected for routing from the next router along a given route if the current processing element node is in a destination global partition or if the current processing element node is one plus or minus hop from reaching the destination global partition and the route is exiting on a port that routes to the destination global partition, else the directions from the global router table are selected for routing from the next router.
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公开(公告)号：EP0734554B1
公开(公告)日：1999-07-14
申请号：EP95905923.9
申请日：1994-12-13
申请人： CRAY RESEARCH, INC.
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing elements memory. A message is a special cache-line-size write that has as its destination a pre-defined queue area in the memory of the receiving processing element. Arriving messages are placed in the queue in the order that they appear at the node by hardware queue management mechanisms. Flow control between processors is usually accomplished by the queue management hardware, with software intervention necessary to deal with the error cases caused by queue overflows, etc.
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公开(公告)号：EP1032887B1
公开(公告)日：2002-03-06
申请号：EP98959468.4
申请日：1998-11-16
申请人： CRAY RESEARCH, INC.
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communications links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and include ports for receiving and sending messages, and lookup tables having a local router table having directions for routing between processor element nodes within a global partition, and a global router table having directions for routing between processor element nodes located in different global partitions. The directions from the local table are selected for routing from the next router along a given route if the current processing element node is in a destination global partition or if the current processing element node is one plus or minus hop from reaching the destination global partition and the route is exiting on a port that routes to the destination global partition, else the directions from the global router table are selected for routing from the next router.
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公开(公告)号：EP1031096A1
公开(公告)日：2000-08-30
申请号：EP98957995.8
申请日：1998-11-16
申请人： CRAY RESEARCH, INC.
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communication links. Routers route messages between processing element nodes on the physical communication links. Each router includes input ports for receiving messages, output ports for sending messages from the router, two types of virtual channels, a lookup table associated with the input port having a lookup table virtual channel number, and a virtual channel assignment mechanism. The virtual channel assignment mechanism assigns an output next virtual channel number for determining the type of virtual channel to be used for routing from a next router along a given route. The next virtual channel number is assigned based on the lookup table virtual channel number and an input next virtual channel number received from a previous router along the given route.
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公开(公告)号：EP0737338A1
公开(公告)日：1996-10-16
申请号：EP95905925.0
申请日：1994-12-13
申请人： CRAY RESEARCH, INC.
CPC分类号： G06F12/1072 , G06F12/0284
摘要： Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.
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公开(公告)号：EP1031085A1
公开(公告)日：2000-08-30
申请号：EP98961737.8
申请日：1998-11-17
申请人： CRAY RESEARCH, INC.
IPC分类号： G06F12/08
CPC分类号： G06F12/0826
摘要： A cache coherence system and method for use in a multiprocessor computer system having a plurality of processors, a memory and an interconnect network connecting the plurality of processors to the memory. The memory includes a plurality of lines and a cache coherence directory structure having a plurality of directory structure entries. Each of the directory structure entries is associated with one of the plurality of lines and each directory structure entry includes processor pointer information, expressed as a set of bit vectors, indicating the processors that have cached copies of lines in memory.
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公开(公告)号：EP0734554A1
公开(公告)日：1996-10-02
申请号：EP95905923.0
申请日：1994-12-13
申请人： CRAY RESEARCH, INC.
IPC分类号： G06F15
CPC分类号： G06F15/17381
摘要： A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing elements memory. A message is a special cache-line-size write that has as its destination a pre-defined queue area in the memory of the receiving processing element. Arriving messages are placed in the queue in the order that they appear at the node by hardware queue management mechanisms. Flow control between processors is usually accomplished by the queue management hardware, with software intervention necessary to deal with the error cases caused by queue overflows, etc.
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公开(公告)号：EP1031096B1
公开(公告)日：2002-07-24
申请号：EP98957995.8
申请日：1998-11-16
申请人： CRAY RESEARCH, INC.
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communication links. Routers route messages between processing element nodes on the physical communication links. Each router includes input ports for receiving messages, output ports for sending messages from the router, two types of virtual channels, a lookup table associated with the input port having a lookup table virtual channel number, and a virtual channel assignment mechanism. The virtual channel assignment mechanism assigns an output next virtual channel number for determining the type of virtual channel to be used for routing from a next router along a given route. The next virtual channel number is assigned based on the lookup table virtual channel number and an input next virtual channel number received from a previous router along the given route.
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公开(公告)号：EP0737338B1
公开(公告)日：2001-02-14
申请号：EP95905925.4
申请日：1994-12-13
申请人： CRAY RESEARCH, INC.
CPC分类号： G06F12/1072 , G06F12/0284
摘要： Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.
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10.发明公开MULTIDIMENSIONAL INTERCONNECTION AND ROUTING NETWORK FOR AN MPP COMPUTER 失效MEHRDIMENZIONALES连接和路由网络MPP计算器
公开(公告)号：EP0733237A1
公开(公告)日：1996-09-25
申请号：EP95905963.0
申请日：1994-12-09
申请人： CRAY RESEARCH, INC.
发明人： BIRRITTELLA, Mark, S. , KESSLER, Richard, E. , OBERLIN, Steven, M. , PASSINT, Randal, S. , THORSON, Creg
CPC分类号： H04L45/06 , G06F15/17337 , G06F15/17381 , H04L45/10 , H04L49/101 , H04L49/205 , H04L49/251
摘要： A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.
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