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公开(公告)号：EP3371833A1
公开(公告)日：2018-09-12
申请号：EP16788549.0
申请日：2016-11-01
IPC分类号： H01L31/0745 , H01L31/0747 , H01L31/18 , H01L31/20
CPC分类号： H01L31/0747 , H01L31/0745 , H01L31/1804 , H01L31/202 , Y02E10/547 , Y02P70/521
摘要： In the present invention a photovoltaic device is proposed comprising: - a silicon-based substrate (2) having a p-type or n-type doping and having a first face; - an intrinsic buffer layer (4) situated on said first face; - a first silicon layer (6) situated on said intrinsic buffer layer (4), said first silicon layer (6) having a doping of a first type being one of p-type doping or n-type doping, said first silicon layer (6) being a patterned layer situated on predetermined regions (4a) of said intrinsic buffer layer (4) and having interstices (5) between said predetermined regions (4a), - a second silicon layer (8) situated on said first silicon layer (6), said second silicon layer (8) having a doping of a second type being the other of the p-type doping or the n- type doping with respect to said doping of said first silicon layer (6); Moreover said photovoltaic device (1) further comprises a third silicon layer (10) situated on said intrinsic buffer layer (4) at said interstices, said third silicon layer (10) being substantially amorphous at least at its side facing said silicon-based substrate (2) and having a doping of said second type
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公开(公告)号：EP3817070A1
公开(公告)日：2021-05-05
申请号：EP19206421.0
申请日：2019-10-31
发明人： FAES, Antonin , PAVIET-SALOMON, Bertrand , BADEL, Nicolas , CHAMPLIAUD, Jonathan , DESPEISSE, Matthieu , BALLIF, Christophe , ANDREATTA, Gaëlle
IPC分类号： H01L31/0224 , H01L31/05 , H01L31/068 , C25D5/02 , H01L21/465 , H01L51/44
摘要： Method of manufacturing a single-side-contacted photovoltaic device (1), comprising the steps of:
a) providing a photovoltaically-active substrate (3) defining a plurality of alternating hole collecting zones (3a) and electron collecting zones (3b) arranged in parallel strips;
b) depositing a conductive layer (5) across said zones;
c) depositing at least one conductive track (9) extending along at least part of each of said zones (3a, 3b);
d) selectively forming a dielectric layer (7) on each of said zones (3a, 3b), so as to leave an exposed area free of dielectric at an interface between adjacent zones (3a, 3b);
e) etching said conductive layer (5) in said exposed areas;
f) applying a plurality of interconnecting conductors (11a, 11b) so as to electrically interconnect at least a portion of said hole collecting zones (3a) with each other, and to electrically interconnect at least a portion of said electron collecting zones (3b) with each other.
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