公开(公告)号：EP4287188A1

公开(公告)日：2023-12-06

申请号：EP22857334.1

申请日：2022-04-29

Applicant: Changxin Memory Technologies, Inc.

Inventor： FAN, Xian ,  GU, Yinchuan ,  CAO, Xianlei ,  YANG, Yu ,  SU, HSIN-CHENG

IPC: G11C11/406 ,  G11C11/409

Abstract: A refresh address counting circuit, a refresh address counting method, a refresh address read-write circuit, and an electronic device, which relate to the technical field of integrated circuits. The refresh address counting circuit comprises: a self-oscillation clock generation module, used for generating, within each refresh cycle, a self-oscillation clock signal based on an array activation signal after a refresh signal is obtained; a self-oscillation mask module, used for generating a self-oscillation mask signal under a preset refresh command; and a refresh address counting module, used for counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and outputting a self-oscillation refresh address. Provided is a refresh address counting circuit suitable for DDR5.

公开(公告)号：EP4198981A1

公开(公告)日：2023-06-21

申请号：EP21922210.6

申请日：2021-07-16

Applicant: Changxin Memory Technologies, Inc.

Inventor： GU, Yinchuan ,  LIU, Geyan

IPC: G11C11/406

Abstract: Embodiments of the present application provide a refresh circuit and a memory. The refresh circuit includes: a refresh control module configured to receive and execute a refresh command to output a row address refresh signal; and further configured to receive a process corner signal to adjust an execution proportion of the refresh command, the faster a process corner represented by the process corner signal, the higher the adjusted execution proportion; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh. The embodiments of the present application help reduce the consumption of refresh currents.

公开(公告)号：EP4325499A1

公开(公告)日：2024-02-21

申请号：EP22940943.8

申请日：2022-09-09

Applicant: Changxin Memory Technologies, Inc.

Inventor： GU, Yinchuan

IPC: G11C11/406

Abstract: Disclosed is a refresh address generation circuit, including: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m, m being an integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, and is configured to pre-store a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address or a second address. The lowest bit of the second address is opposite to that of the first address.

公开(公告)号：EP4328913A1

公开(公告)日：2024-02-28

申请号：EP22941857.9

申请日：2022-11-03

Applicant: Changxin Memory Technologies, Inc.

Inventor： GU, Yinchuan

IPC: G11C11/408

Abstract: The present invention relates to the technical field of semiconductors, and in particular, to a refresh address generation circuit and method, a memory, and an electronic device. The refresh address generation circuit includes a refresh control circuit and an address generator. The refresh control circuit is configured to sequentially receive multiple first refresh commands and perform first refresh operations respectively; output a first clock signal under a condition that the number of the first refresh operations is less than a preset value or output a second clock signal under a condition that the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, pre-stores a first address, receives the first clock signal or the second clock signal, and outputs a first to-be-refreshed address in response to the first clock signal during each of the first refresh operations. The first to-be-refreshed address includes the first address. The address generator changes the first address in response to the second clock signal. A refresh address refreshed by a same bank can be provided.

公开(公告)号：EP4195509A1

公开(公告)日：2023-06-14

申请号：EP21820445.1

申请日：2021-02-09

Applicant: Changxin Memory Technologies, Inc.

Inventor： GU, Yinchuan

IPC: H03K19/08

Abstract: Embodiments of the present application relate to a driving circuit, including: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.

公开(公告)号：EP4060668A1

公开(公告)日：2022-09-21

申请号：EP21867904.1

申请日：2021-07-29

Applicant: Changxin Memory Technologies, Inc.

Inventor： GU, Yinchuan ,  LIU, Geyan

IPC: G11C11/406

Abstract: Embodiments of the present application provide a refresh circuit and a memory. The refresh circuit includes: a refresh control module configured to receive a refresh command to output a row address refresh signal, the row address refresh signal being outputted a number of times of a preset value each time the refresh command is received; and further configured to receive a temperature signal to adjust the preset value, the higher a temperature represented by the temperature signal, the greater the adjusted preset value; a row addresser configured to receive the row address refresh signal and output a to-be-refreshed single-row address; and an array refresh device configured to perform a single-row refresh operation according to the single-row address and output a single-row refresh end signal after the end of single-row refresh. The embodiments of the present application help reduce the consumption of refresh currents.