公开(公告)号：EP1278247A2

公开(公告)日：2003-01-22

申请号：EP02392011.9

申请日：2002-07-15

申请人： Chartered Semiconductor Manufacturing Pte Ltd.

发明人： Lap, Chan ,  Elgin, Quek ,  Ravi, Sundaresan ,  Yang, Pan ,  James, Yong Meng Lee ,  Ying, Keung Leung ,  Yelehanka, Ramachandramurthy Pradeep ,  Jia, Zhen Zheng

IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor subsirate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted Tshaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted Tshaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

摘要翻译： 在半导体器件的气隙垫片的制造方法，包括以下步骤的方法。 提供了一种具有至少一对性病限定有源区的半导体subsirate。 栅电极形成在有源区域内的基材。 具有下面的栅极介电层与栅电极。 衬里氧化物层被形成在该结构上，覆盖栅介电层，在栅电极的侧壁上，并且在栅电极的顶表面。 内衬氮化物层形成在衬垫氧化层。 厚氧化物层被形成在该结构上。 厚氧化层，氮化物衬垫，和衬里氧化物层被平坦化与所述栅电极的顶表面的水平，并暴露在所述栅电极的任一侧上的衬垫氧化层。 平坦化的厚的氧化层与所述衬里氧化物层的一部分，并且在栅电极之下的栅极电介质层的一部分去除，以形成一横截面倒在栅电极一左一右T形开口。 栅极垫片氧化物层被形成在所述结构中的至少一样厚作为栅电极，worin栅极间隔物氧化物层部分地填充从上向下和worin空气间隙的间隔的倒T形开口形成在靠近倒置的底部 T型口。 栅极垫片氧化物，氮化物衬垫，和衬里氧化物层进行蚀刻，形成栅极隔离件邻近所述栅电极。 具有底层的蚀刻衬垫氮化物层和衬垫氧化物层的栅极间隔物。

公开(公告)号：EP1014440A2

公开(公告)日：2000-06-28

申请号：EP99480130.6

申请日：1999-12-16

申请人： Chartered Semiconductor Manufacturing Pte Ltd.

发明人： Lap, Chan ,  Kheng Chok, Tee ,  Kok Keng, Ong ,  Chin Hwee, Seah

IPC分类号： H01L21/768

CPC分类号： H01L21/7682

摘要： A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a "holes everywhere" or a "reverse metal holes" mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.

摘要翻译： 在半导体电路的相邻导线之间通过使用“孔到处”形成气隙的新方法或可用于在电介质层中产生孔的“反向金属孔”掩模。 被蚀刻的电介质已经沉积在导电线之间，以这种方式形成的孔通过在孔的顶部沉积电介质来封闭。 可以在沉积的电介质的整个层上蚀刻孔，或者可以在导电线之间蚀刻孔。

公开(公告)号：EP1278247A3

公开(公告)日：2006-06-14

申请号：EP02392011.9

申请日：2002-07-15

申请人： Chartered Semiconductor Manufacturing Pte Ltd.

发明人： Lap, Chan ,  Elgin, Quek ,  Ravi, Sundaresan ,  Yang, Pan ,  James, Yong Meng Lee ,  Ying, Keung Leung ,  Yelehanka, Ramachandramurthy Pradeep ,  Jia, Zhen Zheng

IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L21/336

CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor subsirate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted Tshaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted Tshaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

公开(公告)号：EP1014440A3

公开(公告)日：2003-11-12

申请号：EP99480130.6

申请日：1999-12-16

申请人： Chartered Semiconductor Manufacturing Pte Ltd.

发明人： Lap, Chan ,  Kheng Chok, Tee ,  Kok Keng, Ong ,  Chin Hwee, Seah

IPC分类号： H01L21/768

CPC分类号： H01L21/7682

摘要： A new method of forming air gaps between adjacent conducting lines of a semiconductor circuit by using a "holes everywhere" or a "reverse metal holes" mask that can be used to create holes in a dielectric layer. The dielectric that is being etched has been deposited across conducting lines, the holes that are being formed in this manner are closed by depositing a dielectric across the top of the holes. The holes can be etched across the entire layer of the deposited dielectric or can be etched in between the conducting lines.