专利检索 ap:("Cisco Technology, Inc.") AND inv:"SMITH, Jane L." 第 1 页

1.

发明公开
AUTOMATED HARDWARE PARITY AND PARITY ERROR GENERATION TECHNIQUE FOR HIGH AVAILABILITY INTEGRATED CIRCUITS 审中-公开
标题翻译：自动化的，硬件奇偶校验错误生产技术集成高可用性CIRCUITS

公开(公告)号：EP2011006A2

公开(公告)日：2009-01-07

申请号：EP07760158.1

申请日：2007-04-05

申请人： Cisco Technology, Inc.

发明人： SMITH, Jane L. , KIRCHENBAUER, Douglas P. , MULLER, Robert A.

IPC分类号： G06F11/00

CPC分类号： G06F11/1032 , G06F11/2247

摘要： A technique wherein High Availability (HA) hardware is used to automatically validate control and configuration registers, e.g. automatically generate parity, detect parity errors, and report errors within software-written configuration and control registers of ASIC and IC products. Parity control logic and Masking Registers are utilized to facilitate automatic parity generation and subsequent parity error reporting. The specific location of where the error occurred can be stored to enable software to correct and/or reconfigure the registers. The HA hardware verifies the validity of control and configuration registers coupled to a bus, utilizing idle cycles in addition to valid bus cycles so there is no impact on system throughput.