公开(公告)号：EP1278133B1

公开(公告)日：2011-11-16

申请号：EP02251559.7

申请日：2002-03-06

申请人： FUJITSU LIMITED

发明人： Abe, Fumirou, c/o Fujitsu Limited ,  Matsuura, Masataka, c/o Fujitsu Limited ,  Tabata, Yoko, c/o Fujitsu Limited ,  Nagata, Masahiko, c/o Fujitsu Kyushu Sys. Eng. Ltd ,  Hara, Yasuhisa, c/o Fujitsu Kyushu Sys. Eng. Ltd

IPC分类号： G06F17/30

CPC分类号： G06F17/30985 ,  G06F11/1032 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99943

公开(公告)号：EP1109321B9

公开(公告)日：2009-11-18

申请号：EP00125557.9

申请日：2000-11-22

申请人： STMicroelectronics SA

发明人： La Rosa, Francesco

IPC分类号： H03M13/19 ,  G06F11/10 ,  G11C29/00

CPC分类号： G06F11/1008 ,  G06F11/1032 ,  G06F2201/81 ,  H03M13/19

摘要： The error correction procedure corrects an error in bit b2 in a sequence of bits b0 - b8. A parity bit (b8) is calculated from the other bits b1 - b7 at an instant where the erroneous bit (b2) was valid, and a second parity bit (b9) calculated from all the bits except the erroneous bit, to replace the erroneous bit.

摘要翻译： 纠错过程纠正b0-b8位序列中的位b2错误。 在错误比特（b2）有效的瞬间从其他比特b1-b7和从除了错误比特以外的所有比特计算出的第二奇偶校验比特（b9）计算奇偶校验位（b8）以代替错误 位。

公开(公告)号：EP1988468A4

公开(公告)日：2009-06-24

申请号：EP06714624

申请日：2006-02-24

申请人： FUJITSU LTD

发明人： KIYOTA NAOHIRO

IPC分类号： G06F12/16 ,  G06F12/08 ,  G06F12/10 ,  G11C29/56

CPC分类号： G11C29/56 ,  G06F11/1032 ,  G11C2029/0407

摘要： To make a diagnosis of all the bits of a RAM in an easier manner at a higher rate regardless of the size of a main memory to be equipped. A bit generating part (110) generates a bit sequence in which a status bit has been added to an upper order of address bits indicative of the addresses of a tag RAM (200a). An increment part (140) increments the bit sequence of the bit generating part (110) by ones. A status selecting part (150) refers to the status bit to select any one of a plurality of processings, and instructs a write control part (160) or a read control part (170) to operate in accordance with the status. The write control part (160) writes in a line of the tag RAM (200a) corresponding to an address bit. The read control part (170) reads from a line of the tag RAM (200a) corresponding to an address bit, and causes the information of this line to be outputted to an error detecting part (180). The error detecting part (180) performs an error check of each line of the tag RAM (200a).

公开(公告)号：EP2011006A2

公开(公告)日：2009-01-07

申请号：EP07760158.1

申请日：2007-04-05

申请人： Cisco Technology, Inc.

发明人： SMITH, Jane L. ,  KIRCHENBAUER, Douglas P. ,  MULLER, Robert A.

IPC分类号： G06F11/00

CPC分类号： G06F11/1032 ,  G06F11/2247

摘要： A technique wherein High Availability (HA) hardware is used to automatically validate control and configuration registers, e.g. automatically generate parity, detect parity errors, and report errors within software-written configuration and control registers of ASIC and IC products. Parity control logic and Masking Registers are utilized to facilitate automatic parity generation and subsequent parity error reporting. The specific location of where the error occurred can be stored to enable software to correct and/or reconfigure the registers. The HA hardware verifies the validity of control and configuration registers coupled to a bus, utilizing idle cycles in addition to valid bus cycles so there is no impact on system throughput.

公开(公告)号：EP1369786A3

公开(公告)日：2005-03-23

申请号：EP03252741.8

申请日：2003-04-30

申请人： Sun Microsystems, Inc.

发明人： Tremblay, Marc ,  Chaudhry, Shailender ,  Jacobson, Quinn A.

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F9/38

CPC分类号： G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

摘要： One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

公开(公告)号：EP1122645A1

公开(公告)日：2001-08-08

申请号：EP98941867.8

申请日：1998-09-14

申请人： FUJITSU LIMITED

发明人： LIN, Chung-hsiung, Fujitsu Digital Tech. Ltd ,  MORIMOTO, Shigeru, Fujitsu Limited

IPC分类号： G06F11/10 ,  G06F12/16

CPC分类号： G06F11/1012 ,  G06F11/1032

摘要： In a memory apparatus using a versatile memory device having no parity function, a memory apparatus fault diagnostic function is implemented with which a written data fault diagnosis is made and upon the memory apparatus faults the data are restorable as much as possible. Input data are parity operated, encoded in a predetermined correlation, and stored in a first address of one memory. The data stored in the first address are then read and the read data are parity operated. The result of the parity operation of the read data is compared with the result of the parity operation of the input data stored in the second address. When a coincidence occurs as a result of this comparison, the data read from the first address are output as valid, whereas when a non-coincidence occurs as a result of this comparison, the encoded data read from the second address are decoded for output.

摘要翻译： 在使用不具有奇偶校验功能的多功能存储装置的存储装置，存储器装置故障诊断功能被实现与一个写入的数据的故障诊断是由和在所述存储装置的故障的数据是可恢复的尽可能。 输入数据被奇偶性操作时，在预定的相关进行编码，并存储在一个存储器中的第一地址。 然后存储在第一地址中的数据被读出并读出的数据是奇偶校验操作。 操作数据的奇偶校验的结果被读出与存储在第二地址中的操作输入数据的奇偶校验的结果相比较。 当一致的发生是由于该比较的结果，从第一地址读出的数据被输出作为有效，而当一个不一致的发生是由于该比较的结果，从所述第二地址读出的编码数据进行解码用于输出。

公开(公告)号：EP0717356A1

公开(公告)日：1996-06-19

申请号：EP94119647.9

申请日：1994-12-13

申请人： BRAIN POWER CO.

发明人： Chan, James

IPC分类号： G06F11/10

CPC分类号： G06F11/1032

摘要： A parity bit memory simulator including a parity bit memory formed of a single bit memory of fixed address length, which replaces the single bit parity RAM of variable address length of conventional memory module, and connected with its address signal line to the data bus of the memory module so that the parity bit memory provides and store parity bits for the computer system without changing the circuit layout of the data memory or caring about the capacity of the memory module. A voltage level detector and a refreshing operation detector can be installed in the parity bit memory to improve the error detecting function of the dynamic random access memory module in the parity bit system.

摘要翻译： 一种奇偶校验位存储器模拟器，包括由固定地址长度的单位存储器形成的奇偶校验位存储器，其替代常规存储器模块的可变地址长度的单位奇偶校验RAM，并将其地址信号线连接到数据总线 使得奇偶校验位存储器为计算机系统提供和存储奇偶校验位，而不改变数据存储器的电路布局或关心存储器模块的容量。 可以在奇偶校验位存储器中安装电压电平检测器和刷新操作检测器，以改进奇偶校验位系统中的动态随机存取存储器模块的错误检测功能。

公开(公告)号：EP0663086A1

公开(公告)日：1995-07-19

申请号：EP93920731.0

申请日：1993-09-15

申请人： SIEMENS TELECOMUNICAZIONI S.P.A.

发明人： DE LEVA, Carlo ,  ZAMBARDI, Maurizio

IPC分类号： G06F11 ,  G11C29

CPC分类号： G06F11/2043 ,  G06F11/1016 ,  G06F11/1032 ,  G06F11/1625 ,  G06F11/1641 ,  G06F11/167 ,  G06F11/2033 ,  G06F11/2097 ,  G11C29/74

摘要： PCT No. PCT/EP93/02496 Sec. 371 Date Mar. 30, 1995 Sec. 102(e) Date Mar. 30, 1995 PCT Filed Sep. 15, 1993 PCT Pub. No. WO94/08292 PCT Pub. Date Apr. 14, 1994A duplicate control and processing unit for telecommunications equipment consisting of two identical control units connected together is described. Each control unit (UC0, UC1) comprises a processing unit (UP0, UP1) which can be active or on standby, a peripheral data random access memory (RAM) for data processed during operation, and several peripheral circuits connected to the rest of the equipment. An EPROM (erasable programmable read-only memory) (CCL0, CCL1) in each processing unit contains the copy selection firmware. The data RAM and the peripheral circuits include a respective double gate access circuit (ACC0, ACC1) which allows selective access to the active processor only. The latter performs the writing cycles synchronously on both the duplicate data RAMs, allowing fast recovery of the operative synchronism by the standby processing unit, after switching due to failure of the active processing unit (FIG. 2).

公开(公告)号：EP1369786B1

公开(公告)日：2006-12-13

申请号：EP03252741.8

申请日：2003-04-30

申请人： SUN MICROSYSTEMS, INC.

发明人： Tremblay, Marc ,  Chaudhry, Shailender ,  Jacobson, Quinn A.

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F9/38

CPC分类号： G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

公开(公告)号：EP1369786A2

公开(公告)日：2003-12-10

申请号：EP03252741.8

申请日：2003-04-30

申请人： Sun Microsystems, Inc.

发明人： Tremblay, Marc ,  Chaudhry, Shailender ,  Jacobson, Quinn A.

IPC分类号： G06F11/10

CPC分类号： G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

摘要： One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

摘要翻译： 本发明的一个实施例提供的系统中的中央处理单元（CPU）内的确在临时结果校正的位错误。 在手术过程中，该系统的飞行指令的执行期间接收临时结果。 接着，系统基因我们获得了临时结果的奇偶校验位，并存储临时结果和在CPU内的临时寄存器的奇偶校验位。 临时结果致力于CPU的架构状态之前，系统会检查临时结果和校验位来检测的位错误。 如果检测到比特错误，系统将执行的微陷阱手术重新执行该指令并生成的临时结果，从而再生临时结果。 否则，如果没有检测到比特错误，系统将提交临时结果到CPU的结构状态。