公开(公告)号：EP2237165A2

公开(公告)日：2010-10-06

申请号：EP10166234.4

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

摘要翻译： 一种包括处理器和可动态配置的通信元件的处理系统，其以散置的布置耦合在一起。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元件。

公开(公告)号：EP2977911A1

公开(公告)日：2016-01-27

申请号：EP15181012.4

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80 ,  G06F15/78

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. Each of said dynamically configurable communication elements further comprises a plurality of input ports and a crossbar coupled to receive data from one or more of said plurality of input ports. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. Each of the dynamically configurable communication elements further comprises a plurality of output registers, wherein its crossbar is further coupled to transmit data to a selected one or more of said plurality of output registers; and wherein each said output register selectively operates in a synchronous data transfer mode or a transparent data transfer mode.

摘要翻译： 一种处理系统，包括处理器和耦合到一起在穿插布置中，可动态配置的通信元件。 每个处理器包括至少一个算术逻辑单元，以指示处理单元和处理器端口复数。 每个动态可配置通信元件包括通信端口复数，一个第一存储器，和一个路由引擎。 每个所述可动态配置的通信元件进一步包括输入端口的多个部分并加以耦合以从一个或多个输入端口中的所述多个接收数据的横梁。 对于每个处理器，处理器端口多元性被配置成耦合到动态可配置的通信元件的所述多个第一子集。 每个动态可配置通信元件进一步包括输出寄存器的复数，worin其横杆还耦合到数据发送到所选择的一个或多个输出寄存器的所述多个; 并且每个worin所述输出寄存器中的同步数据传输模式或透明数据传输模式选择性地操作。

公开(公告)号：EP2237164B1

公开(公告)日：2015-08-19

申请号：EP10165363.2

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/78 ,  G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

公开(公告)号：EP2977911B1

公开(公告)日：2017-11-22

申请号：EP15181012.4

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80 ,  G06F15/78

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

公开(公告)号：EP2224345B1

公开(公告)日：2012-06-20

申请号：EP10164530.7

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

公开(公告)号：EP2237164A3

公开(公告)日：2010-11-10

申请号：EP10165363.2

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

公开(公告)号：EP2239667A3

公开(公告)日：2010-11-10

申请号：EP10168942.0

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

公开(公告)号：EP2237165A3

公开(公告)日：2010-11-10

申请号：EP10166234.4

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

公开(公告)号：EP2224345A3

公开(公告)日：2010-11-03

申请号：EP10164530.7

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

摘要翻译： 处理系统包括处理器和以散布布置耦合在一起的动态可配置通信元件。 每个处理器包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置用于耦合到多个动态可配置通信元件的第一子集。 对于每个可动态配置的通信元件，多个通信端口包括被配置用于耦合到多个处理器的子集的通信端口的第一子集以及被配置用于耦合到多个处理器的第二子集的通信端口的第二子集 动态可配置的通信元件。

公开(公告)号：EP2224345A2

公开(公告)日：2010-09-01

申请号：EP10164530.7

申请日：2003-06-25

申请人： Coherent Logix Incorporated

发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

IPC分类号： G06F15/80

CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

摘要翻译： 一种包括处理器和可动态配置的通信元件的处理系统，其以散置的布置耦合在一起。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元件。