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    SYSTEM WITH INTERSPERSED PROCESSORS AND CONFIGURABLE COMMUNICATION ELEMENTS
    1.
    发明公开
    SYSTEM WITH INTERSPERSED PROCESSORS AND CONFIGURABLE COMMUNICATION ELEMENTS 有权
    与其生产的处理器和浅圆系统组态的通信元件和方法

    公开(公告)号：EP2977911A1

    公开(公告)日：2016-01-27

    申请号：EP15181012.4

    申请日：2003-06-25

    申请人： Coherent Logix Incorporated

    发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

    IPC分类号： G06F15/80 ,  G06F15/78

    CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

    摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. Each of said dynamically configurable communication elements further comprises a plurality of input ports and a crossbar coupled to receive data from one or more of said plurality of input ports. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. Each of the dynamically configurable communication elements further comprises a plurality of output registers, wherein its crossbar is further coupled to transmit data to a selected one or more of said plurality of output registers; and wherein each said output register selectively operates in a synchronous data transfer mode or a transparent data transfer mode.

    摘要翻译： 一种处理系统，包括处理器和耦合到一起在穿插布置中，可动态配置的通信元件。 每个处理器包括至少一个算术逻辑单元，以指示处理单元和处理器端口复数。 每个动态可配置通信元件包括通信端口复数，一个第一存储器，和一个路由引擎。 每个所述可动态配置的通信元件进一步包括输入端口的多个部分并加以耦合以从一个或多个输入端口中的所述多个接收数据的横梁。 对于每个处理器，处理器端口多元性被配置成耦合到动态可配置的通信元件的所述多个第一子集。 每个动态可配置通信元件进一步包括输出寄存器的复数，worin其横杆还耦合到数据发送到所选择的一个或多个输出寄存器的所述多个; 并且每个worin所述输出寄存器中的同步数据传输模式或透明数据传输模式选择性地操作。

    Multiprocessor with specific handling of stalling devices
    2.
    发明授权
    Multiprocessor with specific handling of stalling devices 有权
    与正在进行设备的具体处理多

    公开(公告)号：EP2237164B1

    公开(公告)日：2015-08-19

    申请号：EP10165363.2

    申请日：2003-06-25

    申请人： Coherent Logix Incorporated

    发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

    IPC分类号： G06F15/78 ,  G06F15/80

    CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

    摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

    Transmitting and receiving control information for use with multimedia streams
    3.
    发明公开
    Transmitting and receiving control information for use with multimedia streams 有权
    传输和接收用于多媒体流的控制信息

    公开(公告)号：EP2654266A1

    公开(公告)日：2013-10-23

    申请号：EP13175710.6

    申请日：2009-06-05

    申请人： Coherent Logix Incorporated

    发明人： Shelby, Kevin A. ,  Nysen, Peter J. ,  Doerr, Michael B. ,  McGinn, Colleen J.

    IPC分类号： H04L29/06 ,  H03M13/29

    CPC分类号： H04N21/266 ,  H03M13/1102 ,  H03M13/2732 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2936 ,  H03M13/2957 ,  H03M13/6583 ,  H04L65/4076 ,  H04L65/604 ,  H04L65/607 ,  H04L69/18 ,  H04N21/23605 ,  H04N21/2381 ,  H04N21/4381 ,  H04N21/6112 ,  H04N21/6131

    摘要： First control information, generated according to a first protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. A first data structure specifying that the first control information is of the first protocol version may be generated. A plurality of packets, including a multimedia stream, the first control information, and the first data structure, may be generated and transmitted. Second control information, generated according to a second protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. The first data structure may be modified to include information about the second control information. A second plurality of packets, including the modified first data structure, the first control information, a multimedia stream specified by the first control information, the second control information, and a multimedia stream specified by the second control information, may be generated.

    摘要翻译： 可以生成根据第一协议版本生成的用于配置视听设备以呈现多媒体流的第一控制信息。 可以生成指定第一控制信息是第一协议版本的第一数据结构。 可以生成并发送包括多媒体流，第一控制信息和第一数据结构的多个分组。 可以生成根据第二协议版本生成的用于配置视听设备呈现多媒体流的第二控制信息。 第一数据结构可以被修改以包括关于第二控制信息的信息。 可以生成包括修改后的第一数据结构，第一控制信息，由第一控制信息指定的多媒体流，第二控制信息以及由第二控制信息指定的多媒体流的第二多个分组。

    Transmitting and receiving control information for use with multimedia streams
    6.
    发明公开
    Transmitting and receiving control information for use with multimedia streams 有权
    Senden und Empfangen von Steuerinformationen zur Verwendung mit Multimedia-Streams

    公开(公告)号：EP2439904A1

    公开(公告)日：2012-04-11

    申请号：EP12150157.1

    申请日：2009-06-05

    申请人： Coherent Logix Incorporated

    发明人： Shelby, Kevin A. ,  Nysen, Peter J. ,  Doerr, Michael B. ,  McGinn, Colleen J.

    IPC分类号： H04L29/06 ,  H04L29/08 ,  H04N21/438 ,  H04N21/2381 ,  H03M13/29 ,  H04N21/61

    CPC分类号： H04N21/266 ,  H03M13/1102 ,  H03M13/2732 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2909 ,  H03M13/2936 ,  H03M13/2957 ,  H03M13/6583 ,  H04L65/4076 ,  H04L65/604 ,  H04L65/607 ,  H04L69/18 ,  H04N21/23605 ,  H04N21/2381 ,  H04N21/4381 ,  H04N21/6112 ,  H04N21/6131

    摘要： First control information, generated according to a first protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. A first data structure specifying that the first control information is of the first protocol version may be generated. A plurality of packets, including a multimedia stream, the first control information, and the first data structure, may be generated and transmitted. Second control information, generated according to a second protocol version, for configuring an audiovisual device to present a multimedia stream, may be generated. The first data structure may be modified to include information about the second control information. A second plurality of packets, including the modified first data structure, the first control information, a multimedia stream specified by the first control information, the second control information, and a multimedia stream specified by the second control information, may be generated.

    摘要翻译： 可以生成用于配置视听设备呈现多媒体流的根据第一协议版本生成的第一控制信息。 可以生成指定第一控制信息是第一协议版本的第一数据结构。 可以生成并发送包括多媒体流，第一控制信息和第一数据结构的多个分组。 可以生成用于配置视听设备呈现多媒体流的根据第二协议版本生成的第二控制信息。 可以修改第一数据结构以包括关于第二控制信息的信息。 可以生成包括修改的第一数据结构，第一控制信息，由第一控制信息指定的多媒体流，第二控制信息和由第二控制信息指定的多媒体流的第二多个分组。

    Multiprocessor with specific architecture of communication elements
    7.
    发明公开
    Multiprocessor with specific architecture of communication elements 有权
    Multiprozessorsystem und Herstellungsverfahren mit spezifischer Architektur von Kommunikationselementen

    公开(公告)号：EP2237165A2

    公开(公告)日：2010-10-06

    申请号：EP10166234.4

    申请日：2003-06-25

    申请人： Coherent Logix Incorporated

    发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

    IPC分类号： G06F15/80

    CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

    摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

    摘要翻译： 一种包括处理器和可动态配置的通信元件的处理系统，其以散置的布置耦合在一起。 处理器各自包括至少一个算术逻辑单元，指令处理单元和多个处理器端口。 动态可配置的通信元件各自包括多个通信端口，第一存储器和路由引擎。 对于每个处理器，多个处理器端口被配置为耦合到多个可动态配置的通信元件的第一子集。 对于每个动态可配置的通信元件，多个通信端口包括被配置为耦合到多个处理器的子集的通信端口的第一子集以及被配置为耦合到多个处理器的第二子集的通信端口的第二子集 动态配置的通讯元件。

    SYSTEM WITH INTERSPERSED PROCESSORS AND CONFIGURABLE COMMUNICATION ELEMENTS AND CORRESPONDING MANUFACTURING METHOD
    8.
    发明授权
    SYSTEM WITH INTERSPERSED PROCESSORS AND CONFIGURABLE COMMUNICATION ELEMENTS AND CORRESPONDING MANUFACTURING METHOD 有权
    带有内置处理器和可配置通信元件的系统及相应的制造方法

    公开(公告)号：EP2977911B1

    公开(公告)日：2017-11-22

    申请号：EP15181012.4

    申请日：2003-06-25

    申请人： Coherent Logix Incorporated

    发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

    IPC分类号： G06F15/80 ,  G06F15/78

    CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

    摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

    Multiprocessor with interconnection network using shared memory
    10.
    发明授权
    Multiprocessor with interconnection network using shared memory 有权
    混合处理器和通信元件处理系统

    公开(公告)号：EP2224345B1

    公开(公告)日：2012-06-20

    申请号：EP10164530.7

    申请日：2003-06-25

    申请人： Coherent Logix Incorporated

    发明人： Doerr, Michael B. ,  Hallidy, William H. ,  Gibson, David A. ,  Chase, Craig M.

    IPC分类号： G06F15/80

    CPC分类号： G06F15/80 ,  G06F15/76 ,  G06F15/7867 ,  G06F15/8023 ,  Y02D10/12 ,  Y02D10/13

    摘要： A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.