公开(公告)号：EP3394799A1

公开(公告)日：2018-10-31

申请号：EP16809743.4

申请日：2016-12-07

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： PHILIPPE, Jean-Marc ,  CARBON, Alexandre ,  DURANTON, Marc

IPC分类号： G06N3/063

CPC分类号： G06N3/063

摘要： The circuit comprises at least: a series of calculating blocks that can each implement a group of neurons; and a transformation block (6) which is connected to said calculating blocks by a communication means and can be connected at the input of said circuit to an external data bus (7), said transformation block (6) transforming the format of the input data and transmitting said data to said calculating blocks by means of K independent communications channels (21, 22, 23, 24), an input data word (M1) being cut up into sub-words such that said sub-words are transmitted over a plurality of successive communication cycles, one sub-word being transmitted per communication cycle over a communication channel (21) dedicated to said word (M1) such that said N channels can transmit K words (M1, M2, M3, M4) in parallel.

公开(公告)号：EP3803574A1

公开(公告)日：2021-04-14

申请号：EP19790625.8

申请日：2019-07-09

申请人： COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES

发明人： CATHEBRAS, Joël ,  CARBON, Alexandre ,  SIRDEY, Renaud ,  VENTROUX, Nicolas

IPC分类号： G06F9/30 ,  G06F9/38

公开(公告)号：EP2959382B1

公开(公告)日：2017-06-28

申请号：EP14705764.0

申请日：2014-02-19

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： CARBON, Alexandre ,  LHUILLER, Yves

IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F9/455

CPC分类号： G06F8/443 ,  G06F8/70 ,  G06F9/45504 ,  G06F9/4552

公开(公告)号：EP3803636A1

公开(公告)日：2021-04-14

申请号：EP19790626.6

申请日：2019-07-09

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： CATHEBRAS, Joël ,  CARBON, Alexandre ,  SIRDEY, Renaud ,  VENTROUX, Nicolas

IPC分类号： G06F17/14 ,  G06F9/44

公开(公告)号：EP3394797A1

公开(公告)日：2018-10-31

申请号：EP16806139.8

申请日：2016-12-07

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： CARBON, Alexandre ,  BICHLER, Olivier ,  DURANTON, Marc ,  PHILIPPE, Jean-Marc

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06N3/0481

摘要： The invention relates to a neuron circuit that is capable of producing a weighted sum of digitized input signals and applying an activation function to said weighted sum so as to produce a digitized activation signal as output (40). Said circuit comprises at least: one multiplier (31) multiplying each input signal (x 1 to x n ) with a weight value (w 1j to w nj ), one accumulator (34) accumulating the results of said multiplier so as to produce said weighted sum, and one activation unit (38) executing said activation function. Said activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of said approximated activation function is obtained by one or more arithmetic shifts applied to said weighted sum.

公开(公告)号：EP3005107A1

公开(公告)日：2016-04-13

申请号：EP14725486.6

申请日：2014-05-22

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： CARBON, Alexandre ,  LHUILLIER, Yves ,  CHARLES, Henri-Pierre

IPC分类号： G06F9/455 ,  G06F12/08

CPC分类号： G06F17/30327 ,  G06F9/45516 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/1036 ,  G06F17/30504

摘要： The invention relates to a material accelerator for handling red and black trees, each node of a tree including a binary color indicator, a key, and the addresses of a parent node and of two children nodes, said accelerator including: at least two registers, referred to as node registers (RN1, RN2), for storing the entire data fields of two nodes in a tree; and logic units (UC, UT) configured to receive, from a processor (PROC), at least one input data item selected from a node address in a tree and a so-called reference key and at least one command to be executed; in order to execute said command by combining elementary commands on the data stored in said node registers and to provide the processor with at least one output data item including the address of a node. The invention also relates to a processor and a computer system including such a material accelerator.

公开(公告)号：EP2959382A1

公开(公告)日：2015-12-30

申请号：EP14705764.0

申请日：2014-02-19

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： CARBON, Alexandre ,  LHUILLER, Yves

IPC分类号： G06F9/455 ,  G06F15/02

CPC分类号： G06F8/443 ,  G06F8/70 ,  G06F9/45504 ,  G06F9/4552

摘要： The subject of the invention is a system (304) for compiling at least one instruction flow (303) for its execution on a target circuit (300), the system comprising a hardware acceleration circuit (306) carrying out the functions of loading a set of at least one portion of said flow to an internal memory inside said circuit and of decoding said set; the instructions resulting from the loading and from the decoding being transmitted to a programmable core (307) operating in parallel with the hardware acceleration circuit, said programmable core (307) carrying out the transcription of the decoded instructions into a machine code suitable to be executed on the target circuit (300).

摘要翻译： 用于在目标电路上执行的至少一个指令流的编译系统包括硬件加速电路，其执行将所述流的至少一部分的一组加载到电路内部的存储器并对该组进行解码的功能; 从加载和从解码产生的指令被传送到与硬件加速电路并行操作的可编程内核，可编程核心将解码指令的转录产生为适合在目标电路上执行的机器代码。