摘要:
The invention relates to a method for the on-line testing of pipeline-type devices comprising a succession of stages (121, 122, 123) separated by buffers (111, 112, 113, 114, 115), each buffer (111, 112, 113, 114, 115) being linked to an idle signal, or valid = not idle, and/or at least one status bit. The invention is characterised in that it combines at least the following steps: a) detecting the values of the idle signal and/or the corresponding status bits representing the non-use of a cycle or a sudden interruption to the operation flow in a pipeline, and indicating that an operation (O3) executed by a stage of the pipeline, known as a valid operation, is monitored by a non-used cycle; b) maintaining the status of the buffer (111) in order to allow the re-execution of the valid operation (O3) during the non-used cycle indicated by the idle signal; c) during the non-used cycle, re-executing the valid operation (O3) in order to obtain at least a first version (O'3) and a second version (O"3) of the valid operation (O3); d) at the pipeline output, recording the results corresponding to the first version (O'3) of said replicated or re-executed operation (O3) in order to compare same to the results of the second version (O"3) of the same replicated or re-executed operation (O3); and e) comparing the results obtained at the pipeline output, corresponding to the first version (O'3) and to the second version (O"3) and, in the event of a difference, indicating the presence of an error.
摘要:
La présente invention concerne un procédé d'écriture d'un mot de données dans une mémoire résistive composée de cellules différentielles 2T2R comprenant chacune des premier et deuxième ensembles d'un résistor (R) et d'un transistor de sélection (T). Le procédé comprend des étapes consistant à générer un mot de code initial, le programmer en mode 1T1R, vérifier sa programmation en mode 1T1R, l'inverser, programmer en mode 1T1R le mot de code initial inversé, vérifier en mode 1T1R sa programmation, et lire en mode différentiel 2T2R que les données lues correspondent auxdites données initiales. La présente invention concerne également un dispositif adapté pour mettre en œuvre ce procédé d'écriture et un système électronique comprenant ce dispositif.
摘要:
L'invention concerne une solution pour améliorer la correction d'erreurs dans une mémoire résistive 2T2R protégée par un code correcteur d'erreur. De manière générale, le principe de l'invention repose sur un procédé qui permet par des lectures 1T1R d'identifier dans un mot de code stocké en mémoire, des bits susceptibles d'être erronés dits « erasures », puis d'inverser ces bits dans le mot de code stocké afin de générer un nouveau mot corrigé par l'ECC.
摘要:
A method for protecting digital memory against permanent and transient errors and a related device, the digital data being stored in at least one storage matrix of memory cells in a given number of rows and columns, comprises: an encoding step generating code words from data organized in binary words by application of asymmetric code introducing at least two different levels of protection, the first level of protection said to be high being associated with a first sub-group of bits of the code word and a second level of protection said to be low being associated with a second sub-group of the same word; swapping positions of the bits of the code word making the bits with a high level of protection correspond for their storage to the columns of the storage area comprising defective memory cells and the bits with a low level of protection to the remaining columns.