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公开(公告)号：EP0389001B1
公开(公告)日：1997-06-04
申请号：EP90109463.1
申请日：1984-04-18
申请人： CRAY RESEARCH, INC.
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3879 , G06F13/18 , G06F15/17 , G06F15/8092
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公开(公告)号：EP0389001A2
公开(公告)日：1990-09-26
申请号：EP90109463.1
申请日：1984-04-18
申请人： CRAY RESEARCH, INC.
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3879 , G06F13/18 , G06F15/17 , G06F15/8092
摘要： A multiprocessing system and method for multiprocessing disclosed. A pair of processors (10,11) are provided, and each are connected to a central memory (12) through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers (50) which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit (290) which senses and prioritizes conflicting references to the central memory between the CPU (20). Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and faciliates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
摘要翻译： 一种用于多处理的多处理系统和方法。 提供一对处理器（10,11），并且每个处理器（10,11）通过多个存储器参考端口连接到中央存储器（12）。 处理器还每个连接到多个共享寄存器（50），其可以由两个处理器以与处理器内操作相称的速率直接寻址。 共享寄存器包括用于保存标量和地址信息的寄存器以及用于保存用于协调通过共享寄存器传送信息的信息的寄存器。 提供多端口存储器并且包括冲突解决电路（290），其检测并优先化CPU（20）之间对中央存储器的冲突引用。 每个CPU通过三个端口与中央存储器连接，每个端口处理可以进行的几种不同类型的存储器引用的不同的端口。 提供至少一个I / O端口以由处理器在中央存储器和外围存储设备之间传送信息时共享。 还公开了用于向量处理计算机中的向量寄存器设计，并为向量数据提供至少两个可独立寻址的存储器用于传递到功能单元或从功能单元接收。 多处理方法允许多处理器中的多任务处理，其中共享寄存器允许单个作业的不同作业或相关任务的独立任务并行运行，并且通过允许多个关键代码区域独立同步来便于操作系统的多线程 。
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公开(公告)号：EP0389001A3
公开(公告)日：1991-12-04
申请号：EP90109463.1
申请日：1984-04-18
申请人： CRAY RESEARCH, INC.
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3879 , G06F13/18 , G06F15/17 , G06F15/8092
摘要： A multiprocessing system and method for multiprocessing disclosed. A pair of processors (10,11) are provided, and each are connected to a central memory (12) through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers (50) which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit (290) which senses and prioritizes conflicting references to the central memory between the CPU (20). Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and faciliates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
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公开(公告)号：EP0123509A2
公开(公告)日：1984-10-31
申请号：EP84302632.9
申请日：1984-04-18
申请人： Cray Research, Inc.
IPC分类号： G06F15/16 , G06F15/347
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3879 , G06F13/18 , G06F15/17 , G06F15/8092
摘要： A multiprocessing system and method for multiprocessing disclosed. A pair of processors (10,11) are provided, and each are connected to a central memory (12) through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers (50) which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit (290) which senses and prioritizes conflicting references to the central memory between CPU (20). Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one t/0 port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
摘要翻译： 两个处理器（10,11）中的每一个具有到中央存储器（12）的数据（13,14）和控制路径（15,16）。 相应的控制路径（21,22）将每个处理器连接到通过双向数据路径（23）连接到存储器的CPU输入输出控制（20）。 存储器被布置在交织的存储体中，用于在每个机器时钟周期期间进行独立的并行访问。 处理器之间的相互通信是通过具有在处理器的共同控制下的共享寄存器的通信和控制电路（50），并且可以通过相应数据路径（51,52）从任一个CPU读取或写入。 数据传输通过电路（50）寄存器或中央存储器由信号量寄存器进行协调。
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公开(公告)号：EP0123509B1
公开(公告)日：1992-04-08
申请号：EP84302632.9
申请日：1984-04-18
申请人： Cray Research, Inc.
IPC分类号： G06F15/16 , G06F15/347
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3879 , G06F13/18 , G06F15/17 , G06F15/8092
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公开(公告)号：EP0123509A3
公开(公告)日：1988-04-27
申请号：EP84302632
申请日：1984-04-18
申请人： Cray Research, Inc.
IPC分类号： G06F15/16 , G06F15/347
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3879 , G06F13/18 , G06F15/17 , G06F15/8092
摘要： A multiprocessing system and method for multiprocessing disclosed. A pair of processors (10,11) are provided, and each are connected to a central memory (12) through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers (50) which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit (290) which senses and prioritizes conflicting references to the central memory between CPU (20). Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one t/0 port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
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