公开(公告)号：EP1032887B1

公开(公告)日：2002-03-06

申请号：EP98959468.4

申请日：1998-11-16

申请人： CRAY RESEARCH, INC.

发明人： PASSINT, Randal, S. ,  GALLES, Michael, B. ,  THORSON, Greg

IPC分类号： G06F15/173

CPC分类号： G06F15/17381

摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communications links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and include ports for receiving and sending messages, and lookup tables having a local router table having directions for routing between processor element nodes within a global partition, and a global router table having directions for routing between processor element nodes located in different global partitions. The directions from the local table are selected for routing from the next router along a given route if the current processing element node is in a destination global partition or if the current processing element node is one plus or minus hop from reaching the destination global partition and the route is exiting on a port that routes to the destination global partition, else the directions from the global router table are selected for routing from the next router.

公开(公告)号：EP1031096A1

公开(公告)日：2000-08-30

申请号：EP98957995.8

申请日：1998-11-16

申请人： CRAY RESEARCH, INC.

发明人： PASSINT, Randal, S. ,  THORSON, Greg ,  GALLES, Michael, B.

IPC分类号： G06F15/173

CPC分类号： G06F15/17381

摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communication links. Routers route messages between processing element nodes on the physical communication links. Each router includes input ports for receiving messages, output ports for sending messages from the router, two types of virtual channels, a lookup table associated with the input port having a lookup table virtual channel number, and a virtual channel assignment mechanism. The virtual channel assignment mechanism assigns an output next virtual channel number for determining the type of virtual channel to be used for routing from a next router along a given route. The next virtual channel number is assigned based on the lookup table virtual channel number and an input next virtual channel number received from a previous router along the given route.

公开(公告)号：EP0969380A3

公开(公告)日：2000-02-02

申请号：EP99117731.2

申请日：1991-06-10

申请人： CRAY RESEARCH, INC.

发明人： Wengelski, Diane M. ,  Gaertner, Gregory G.

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F9/4881 ,  G06F8/41 ,  G06F8/433 ,  G06F8/445 ,  G06F8/45 ,  G06F9/5016 ,  G06F12/023 ,  G06F12/08 ,  G06F12/109 ,  G06F12/12

摘要： The present invention provides a parallel memory scheduler (1120) for execution on a high speed parallel multiprocessor architecture (10). The operating system software provides intelligence and efficiency in swapping out process images to facilitate swapping in another process. The splitting and coalescing of data segments are used to fit segments into current free memory (50) even though a single contiguous space of sufficient size does not exist. Mapping these splits through data control register sets (80) retains the user's contiguous view of the address space. The existence of dual images (14, 70) and partial swapping allows efficient, high speed swapping. Candidates for swap (150, 160, 170) our are chosen in an intelligent fashion, selecting only those candidates which will most efficiently allow the swapin of another process.

公开(公告)号：EP0969380A2

公开(公告)日：2000-01-05

申请号：EP99117731.2

申请日：1991-06-10

申请人： CRAY RESEARCH, INC.

发明人： Wengelski, Diane M. ,  Gaertner, Gregory G.

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F9/4881 ,  G06F8/41 ,  G06F8/433 ,  G06F8/445 ,  G06F8/45 ,  G06F9/5016 ,  G06F12/023 ,  G06F12/08 ,  G06F12/109 ,  G06F12/12

摘要： The present invention provides a parallel memory scheduler (1120) for execution on a high speed parallel multiprocessor architecture (10). The operating system software provides intelligence and efficiency in swapping out process images to facilitate swapping in another process. The splitting and coalescing of data segments are used to fit segments into current free memory (50) even though a single contiguous space of sufficient size does not exist. Mapping these splits trough data control register sets (80) retains the user's contiguous view of the address space. The existence of dual images (14, 70) and partial swapping allows efficient, high speed swapping. Candidates for swap (150, 160, 170) our are chosen in an intelligent fashion, selecting only those candidates which will most efficiently allow the swapin of another process.

摘要翻译： 本发明提供了用于在高速并行多处理器架构（10）上执行的并行存储器调度器（1120）。 操作系统软件提供了更换过程映像的智能和效率，以便于在另一个过程中进行交换。 即使没有足够大小的单一连续空间，数据段的拆分和合并也被用于将段适配到当前空闲存储器（50）中。 通过数据控制寄存器组（80）映射这些分割保留了用户对地址空间的连续视图。 双图像（14,70）的存在和部分交换允许有效的高速交换。 互换的候选人（150,160,170）我们是以智能的方式选择的，只选择那些最有效地允许另一个过程互换的候选人。

公开(公告)号：EP0535107B1

公开(公告)日：1999-12-08

申请号：EP91911933.9

申请日：1991-06-10

申请人： CRAY RESEARCH, INC.

发明人： RASBOLD, James, C. ,  VAN DYKE, Don, A.

IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F9/30

CPC分类号： G06F8/41 ,  G06F8/433 ,  G06F8/445 ,  G06F8/45 ,  G06F12/023 ,  G06F12/08 ,  G06F12/12

摘要： A method for scheduling instructions for a processor having multiple functional resources wherein the reordering of the instructions is acomplished in response to a simulation of the run-time environment of the target machine. The simulation of the run-time environment of the target machine is performed at compile time after the machine instructions have been generated by a compiler, or after instruction generation by an assembler. The present invention rearranges the machine instructions for a basic block (10) of instructions into an order that will result in the fastest execution based upon the results of the simulation of the interaction of the multiple functional resources in the target machine.

公开(公告)号：EP0797803A1

公开(公告)日：1997-10-01

申请号：EP95944840.0

申请日：1995-08-01

申请人： CRAY RESEARCH, INC.

发明人： LEEDOM, George W. ,  MOORE, William T.

IPC分类号： G06F17 ,  G06F9 ,  G06F15

CPC分类号： G06F15/8084 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3836

摘要： Method and apparatus for vector processing on a computer system. As the last element of a group of elements (called a 'chunk') in a vector register is loaded from memory, the entire chunk is marked valid and thus made available for use by subsequent or pending operations. The vector processing apparatus comprises a plurality of vector registers, wherein each vector register holds a plurality of elements. For each of the vector registers, a validity indicator is provided wherein each validity indicator indicates a subset of the elements in the corresponding vector register which are valid. A chunk-validation controller is coupled to the validity indicators operable to adjust a value of the validity indicator in response to a plurality of elements becoming valid. An arithmetic logical functional unit (ALFU) is coupled to the vector registers to execute functions specified by program instructions. A vector register controller is connected to control the vector registers in response to program instructions in order to cause valid elements of a selected vector register to be successively transmitted to said ALFU, so that elements are streamed through said ALFU at a speed that is determined by the availability of valid elements from the vector registers. The ALFU optionally comprises a processor pipeline to hold operand data for operations not yet completed while receiving operands for successive operations. The ALFU also optionally comprises an address pipeline to hold element addresses corresponding to the operands for operations not yet completed while receiving element addresses corresponding to the operands for successive operations.

公开(公告)号：EP0792486A1

公开(公告)日：1997-09-03

申请号：EP95923926.0

申请日：1995-06-16

申请人： CRAY RESEARCH, INC.

发明人： WEST, Jeffrey, D.

IPC分类号： G01R31

CPC分类号： G01R31/318552

摘要： A test access port controller for use in a level sensitive scan design having test design logic including at least one serial scan test path. The test access port controller includes test access port controller logic operable in a system test mode for controlling the serial shifting of input test data into the at least one serial scan test path and for controlling serial shifting of resulting output test data out of the at least one serial scan test path after performance of system mode test under control of a test clock. The test access port controller further includes clock logic for providing the test clock to the test access port controller logic and the test design logic in system test mode. The clock logic further provides a system clock to the test access port controller logic and test design logic in a fabrication test mode to serially shift input test data into the test access port controller logic and test design logic and to serially shift resulting output data out of the test access port controller logic and test design logic after operation of the test access port controller logic and test design logic under one cycle of test clock. A test method for such level sensitive scan designs includes serially shifting input test data into the test access port controller and the test design logic under control of the system clock. Then the test access port controller is operated under control of the test clock for at least one cycle to generate resulting output test data. The resulting output test data is serially shifted out of the test access port controller and the test design logic under control of the system clock.

公开(公告)号：EP0571395B1

公开(公告)日：1997-07-30

申请号：EP92901473.6

申请日：1991-11-22

申请人： CRAY RESEARCH, INC.

发明人： SCHIFFLEGER, Alan, J.

IPC分类号： G06F15/16 ,  G06F9/46

CPC分类号： G06F9/52 ,  G06F9/526 ,  G06F15/167

摘要： A tightly coupled communication scheme based on a common shared resource circuit and adapted particularly to a multiprocessing system including 2N CPUs. A mechanism has been added that allows data in a shared register to be read and incremented as a single instruction, eliminating the need for semaphore manipulations during the operation. A second mechanism has been added to permit the use of indirect addressing in the addressing of semaphore bits and shared registers. Operating systems can relocate semaphore bits and message areas to permit simultaneous execution of the same function within a single task. In addition, an instruction has been added which tests of the semaphore bit and acts upon the state of that bit. If the semaphore bit is not set then the processor takes control of the semaphore bit by setting it. If the semaphore bit is set, the processor will execute a branch and execute other instructions. Thus, jobs assigned to a processor in a multiprocessing, multitasking application do not block or wait for the semaphore bit to clear.

公开(公告)号：EP0737338A1

公开(公告)日：1996-10-16

申请号：EP95905925.0

申请日：1994-12-13

申请人： CRAY RESEARCH, INC.

发明人： OBERLIN, Steven, M. ,  FROMM, Eric, C. ,  PASSINT, Randal, S.

IPC分类号： G06F15 ,  G06F12

CPC分类号： G06F12/1072 ,  G06F12/0284

摘要： Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining logical addresses for PE's and memory within a three-dimensional interconnected network of PE's in the MPP, and physical addresses for PE's and memory corresponding to identities and locations of PE modules within computer cabinetry. As physical PE's are mapped into or out of the logical MPP, as spares are needed, logical addresses are updated. Address references generated by a PE within a partition in virtual address mode are converted to logical addresses and physical addresses for routing on the network.

公开(公告)号：EP0712076A2

公开(公告)日：1996-05-15

申请号：EP96200086.5

申请日：1991-11-22

申请人： CRAY RESEARCH, INC.

发明人： Schiffleger, Alan J.

IPC分类号： G06F9/46 ,  G06F15/16

CPC分类号： G06F9/52 ,  G06F9/526 ,  G06F15/167

摘要： A tightly coupled communication scheme based on a common shared resource circuit and adapted particularly to a multiprocessing system including 2 N CPUs. A mechanism has been added that allows data in a shared register to be read and incremented as a single instruction, eliminating the need for semaphore manipulations during the operation. A second mechanism has been added to permit the use of indirect addressing in the addressing of semaphore bits and shared registers. Operating systems can relocate semaphore bits and message areas to permit simultaneous execution of the same function within a single task. In addition, an instruction has been added which tests of the semaphore bit and acts upon the state of that bit. If the semaphore bit is not set then the processor takes control of the semaphore bit by setting it. If the semaphore bit is set, the processor will execute a branch and execute other instructions. Thus, jobs assigned to a processor in a multiprocessing, multitasking application do not block or wait for the semaphore bit to clear.

摘要翻译： 基于公共共享资源电路的紧耦合通信方案，并且特别适用于包括2N个CPU的多处理系统。 增加了一种机制，允许共享寄存器中的数据作为单条指令读取和增加，消除了操作期间对信号量操作的需要。 增加了第二种机制，允许在寻址信号位和共享寄存器时使用间接寻址。 操作系统可以重新定位信号位和消息区域，以允许在单个任务中同时执行相同的功能。 此外，还添加了一条指令，对信号量位进行哪些测试并根据该位的状态进行操作。 如果没有设置信号量位，则处理器通过设置来控制信号量位。 如果信号位被置位，处理器将执行一个分支并执行其他指令。 因此，分配给多处理多任务应用程序中处理器的作业不会阻塞或等待信号量位清除。