SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL
    5.
    发明公开
    SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL 审中-公开
    高性能半导体沟道COMPONENT

    公开(公告)号:EP2681769A1

    公开(公告)日:2014-01-08

    申请号:EP12701557.6

    申请日:2012-01-06

    申请人: Cree, Inc.

    IPC分类号: H01L29/10

    摘要: Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

    TRANSISTORS WITH A GATE INSULATION LAYER HAVING A CHANNEL DEPLETING INTERFACIAL CHARGE AND RELATED FABRICATION METHODS
    7.
    发明公开
    TRANSISTORS WITH A GATE INSULATION LAYER HAVING A CHANNEL DEPLETING INTERFACIAL CHARGE AND RELATED FABRICATION METHODS 审中-公开
    具有栅极绝缘层的晶体管具有去除界面电荷的通道和相关的制造方法

    公开(公告)号:EP2502261A1

    公开(公告)日:2012-09-26

    申请号:EP10726769.2

    申请日:2010-06-22

    申请人: Cree, Inc.

    摘要: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.

    摘要翻译: 金属 - 绝缘体 - 半导体场效应晶体管(MISFET)包括具有第一导电类型的源极和漏极区域的SiC层。 第一栅极绝缘层在SiC层上并且沿与SiC层的界面具有净电荷,该极性与源极区的多数载流子具有相同的极性。 栅极触点位于源极和漏极区域之间的SiC层的沟道区上的第一栅极绝缘层上。 沿着所述第一栅绝缘层和SiC层可以由在SiC层的源和漏区之间的沟道区的相邻部分,这可以增加MISFET和/的阈值电压耗尽多数载流子之间的界面处的净电荷 或增加其中的电子迁移率。