SERIAL MAGNETIC LOGIC UNIT ARCHITECTURE
    2.
    发明公开
    SERIAL MAGNETIC LOGIC UNIT ARCHITECTURE 审中-公开
    ARCHITEKTURFÜRMAGNETISCHE SERIELLE LOGISCHE EINHEIT

    公开(公告)号:EP3152765A1

    公开(公告)日:2017-04-12

    申请号:EP15802692.2

    申请日:2015-06-03

    IPC分类号: G11C19/00

    摘要: An apparatus has magnetic logic units a logic circuit configured to receive a serial input bit stream at an input node. Individual bits of data from the serial input bit stream are serially written into individual magnetic logic units without buffering the serial input bit stream between the input node and the individual magnetic logic units. Individual bits of data from individual magnetic logic units are serially read to produce a serial output bit stream on an output node without buffering the serial output bit stream between the individual magnetic logic units and the output node.

    摘要翻译: 一种装置具有磁逻辑单元,逻辑电路被配置为在输入节点处接收串行输入位流。 来自串行输入比特流的单独的数据位被串行地写入单个磁逻辑单元,而不在输入节点和各个逻辑单元之间缓冲串行输入比特流。 串行读取来自各个逻辑单元的单独的数据位,以在输出节点上产生串行输出比特流,而不会在各个逻辑单元与输出节点之间缓冲串行输出比特流。