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公开(公告)号：EP4390622A1
公开(公告)日：2024-06-26
申请号：EP23214337.0
申请日：2023-12-05
发明人： JUN, Sang Hun , KI, Yang Seok
CPC分类号： G06F1/263 , G06F1/189 , G06F1/187 , G11C5/141 , G11C5/143 , G06F13/4068 , G06F13/1668 , G06F3/0673 , G06F3/0619 , G06F3/0653
摘要： Provided is an apparatus comprising a storage device comprising: an interface to connect the storage device to a storage system; and a power control circuit configured to control a power transfer to the storage device; wherein the power control circuit is configured to control a power transfer to a power device. Provided is further an apparatus comprising:
a power device comprising an interface to connect the power device to a storage system;
a power source; and a power control circuit configured to control, at least partially, a power transfer from the power source to a storage device; wherein at least a portion of the power device has a storage device form. A method comprises performing, at a storage structure, a power transfer with a storage device and a power device, wherein the power transfer is controlled, at least partially, by a power control circuit located, at least partially, at the storage device or the power device.-
公开(公告)号：EP2936496B1
公开(公告)日：2018-11-28
申请号：EP12890251.7
申请日：2012-12-21
发明人： TREZISE, Gregory , HANA, Andrew
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F3/0683 , G06F11/1052 , G11C5/04 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： A memory module includes an error correction logic to provide data error protection for data stored in the memory module. The error correction logic is selectively controllable between an enabled state and a disabled state. Data stored in the memory module is without error protection provided by the memory module if the error correction logic is in the disabled state.
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公开(公告)号：EP3387513A1
公开(公告)日：2018-10-17
申请号：EP16874038.9
申请日：2016-12-12
申请人： Vivante Corporation
发明人： LO, Mankit
IPC分类号： G06F3/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F5/12
摘要： A computer system includes a hardware buffer controller. Memory access requests to a buffer do not include an address within the buffer and threads accessing the buffer do not access or directly update any pointers to locations within the buffer. The memory access requests are addressed to the hardware buffer controller, which determines an address from its current state and issues a memory access command to that address. The hardware buffer controller updates its state in response to the memory access requests. The hardware buffer controller evaluates its state and outputs events to a thread scheduler in response to overflow or underflow conditions or near-overflow or near-underflow conditions. The thread scheduler may then block threads from issuing memory access requests to the hardware buffer controller. The buffer implemented may be a FIFO or other type of buffer.
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公开(公告)号：EP2943956B1
公开(公告)日：2018-10-03
申请号：EP14702117.4
申请日：2014-01-07
发明人： SHEN, Jian , WANG, Liyong , CHUA-EOAN, Lew
IPC分类号： G11C7/10 , G11C11/408 , G11C11/4093
CPC分类号： G11C8/18 , G06F3/0604 , G06F3/0638 , G06F3/0653 , G06F3/0673 , G06F12/0215 , G06F12/0802 , G06F12/0862 , G06F12/10 , G06F13/1689 , G06F2212/1016 , G06F2212/60 , G11C7/1039 , G11C8/06 , G11C8/10 , G11C11/4082 , G11C11/4093
摘要： A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.
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公开(公告)号：EP3379423A1
公开(公告)日：2018-09-26
申请号：EP18152857.1
申请日：2018-01-22
申请人： INTEL Corporation
CPC分类号： G06F3/0653 , G06F3/0616 , G06F3/0656 , G06F3/0673 , G06F12/0284 , G06F13/1673 , G06F13/28
摘要： Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.
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公开(公告)号：EP2740038B1
公开(公告)日：2018-09-19
申请号：EP11870564.9
申请日：2011-08-04
申请人： Intel Corporation
CPC分类号： G06F3/0608 , G06F3/0644 , G06F3/0673 , G06F12/023 , G06F2212/1044
摘要： Embodiments of computer-implemented methods, apparatus and computer-readable media associated with memory management are disclosed herein. A computer-implemented method to coalesce free intervals of a memory may include ascertaining that a first interval of the memory is free (302, 304). A determination may be made, e.g., from a header associated with the first interval of the memory, whether a second interval of the memory, immediately preceding or following the first interval of the memory, is free (306). After a determination is made that the second interval of the memory is free, the first interval of the memory and the second interval of the memory may be coalesced (310). Other embodiments may be described and/or claimed.
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公开(公告)号：EP3350683A1
公开(公告)日：2018-07-25
申请号：EP16847431.0
申请日：2016-09-16
发明人： LI, Shu , LI, Yong , NIU, Gongbiao
IPC分类号： G06F3/06
CPC分类号： G06F3/0641 , G06F3/0608 , G06F3/0611 , G06F3/0673 , G06F3/0679 , G06F13/42 , G06F2213/0032
摘要： A data deduplication method is executed by a controller for a solid state drive (SSD). The controller receives a signature for a block of data. The controller performs a comparison of the signature and information in a signature library and determines whether or not the signature matches the information. The controller sends a signal that indicates a result of the comparison. If the signature and the information match then the signal has a first value indicating that the block of data is already stored on the SSD; if the signature and the information do not match then the signal has a second value that is different than the first value.
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公开(公告)号：EP2807583B1
公开(公告)日：2018-07-25
申请号：EP12707661.0
申请日：2012-01-24
发明人： FAITELSON, Yakov , KORKUS, Ohad , BASS, David , KAYSAR, Yzhar , GOLDSTEIN, Doron , DAVID, Oren
IPC分类号： G06F17/30
CPC分类号： G06F17/30144 , G06F3/0614 , G06F3/0653 , G06F3/0673 , G06F17/30091
摘要： A computerized method and apparatus for distinguishing between false positive read events and true positive events of reading a file, comprising determining an amount of date read from the file, in case the amount of data exceeds a threshold generating a true positive read event, otherwise generating a false positive read event in case a decision condition is met, and an apparatus to carry out the same.
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公开(公告)号：EP2802110B1
公开(公告)日：2018-07-11
申请号：EP14167804.5
申请日：2014-05-09
IPC分类号： G06F3/06
CPC分类号： G06F3/065 , G06F3/0614 , G06F3/0638 , G06F3/0673 , G06F12/1027 , G06F17/30097 , G06F2003/0691 , G06F2212/507 , H04L45/7453
摘要： A method and apparatus of a device that reads and writes data using a shared memory hash table and a lookaside buffer is described. In an exemplary embodiment, a device locates a bucket for the data in a shared memory hash table, where a writer updates the shared memory hash table and a reader that is one of a plurality of readers reads from the shared memory hash table. The device further retrieves an initial value of a version of the bucket. If the initial value of the version is odd, the device copies the data from a lookaside buffer of the writer to a local buffer for the reader, wherein the lookaside buffer stores a copy of the data while the bucket is being modified.
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10.发明公开
公开(公告)号：EP3343383A1
公开(公告)日：2018-07-04
申请号：EP17207175.5
申请日：2017-12-13
申请人： INTEL Corporation
发明人： VENKATESH, Ganesh , MARR, Deborah
IPC分类号： G06F13/16
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0637 , G06F3/0638 , G06F3/0673 , G06F12/0646 , G06F13/1663 , G06F2212/1016 , G06N99/005 , Y02D10/14
摘要： Techniques for enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies are disclosed. A hardware processor includes a plurality of processing elements, a memory that is heavily-banked into a plurality of banks, and an arbiter. The arbiter is to receive requests from threads executing at the plurality of processing elements seeking to perform operations involving the memory, and to maintain a plurality of lock buffers corresponding to the plurality of banks. Each of the lock buffers is able to track up to a plurality of memory addresses within the corresponding bank that are to be treated as locked in that the values stored at those memory addresses cannot be updated by those of the threads that did not cause the memory addresses to be locked until those memory addresses have been removed from being tracked by the plurality of lock buffers.
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