Register and instruction controller for superscalar processor
    1.
    发明公开
    Register and instruction controller for superscalar processor 失效
    注册和Befehlssteuerungfüreinen superskalaren Prozessor

    公开(公告)号:EP0767425A3

    公开(公告)日:1998-07-08

    申请号:EP96307288

    申请日:1996-10-04

    IPC分类号: G06F9/30 G06F9/38

    摘要: In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. The plurality of sets are disjoint according to the addresses of the data to be accessed by the instructions while executing in the superscalar computer system. The system includes a plurality of clusters for executing the instructions. There is one cluster for each one of the plurality of sets of instructions. Each set of instructions is distributed to the plurality of clusters so that the addresses of the data accessed by the instructions are substantially disjoint among the clusters while immediately executing the instructions. This partitioning and distributing minimizes the number of interconnects between the clusters of the superscalar computer.

    摘要翻译: 在超标量计算机系统中,同时执行多个指令。 正在执行的指令访问存储在超标量计算机系统的地址处的数据。 诸如编译器的指令生成器将指令分成多个集合。 根据在超标量计算机系统中执行时由指令访问的数据的地址,多个集合是不相交的。 该系统包括用于执行指令的多个簇。 对于多组指令中的每一组,存在一个集群。 每组指令被分配到多个簇,使得由指令访问的数据的地址在立即执行指令之间在簇之间基本上不相交。 这种分配和分发使超标量计算机的集群之间的互连数量最小化。