公开(公告)号：EP0601823A1

公开(公告)日：1994-06-15

申请号：EP93309789.1

申请日：1993-12-06

申请人： DIGITAL EQUIPMENT CORPORATION

发明人： Mistry, Kaizad R.

IPC分类号： H01L27/02 ,  H01L29/56

CPC分类号： H01L29/1087 ,  H01L21/28537 ,  H01L27/0255 ,  H01L29/7839

摘要： A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs. The clamping performed by the invention reduces wearout and other deleterious effects of excess voltage.

摘要翻译： MOSFET器件采用集成的肖特基二极管钳位源，连接在源极或漏极端子与散装端子之间。 在说明性实施例中，在位于p型硅衬底中的n阱中形成一个或多个MOSFET。 每个漏极由金属硅化物层的一部分下面的p +区形成。 在一个实施例中，p +区域位于金属硅化物的边缘的下方; 在另一个实施例中，p +区域位于金属硅化物的相对边缘的下方，使得金属硅化物的一部分接触n-阱。 每个源由金属硅化物层下面的p +区形成。 每个栅极包括一层由金属硅化物层包覆的p +或n +多晶硅层，栅极通过一层氧化物与n阱分离。 与p-n结二极管相比，集成肖特基二极管更有效地限制了施加到MOSFET的过电压。 本发明的钳位减少了过电压的损耗和其他有害影响。