-
公开(公告)号：EP1518246B1
公开(公告)日：2006-07-12
申请号：EP03724302
申请日：2003-04-29
CPC分类号： G11C11/16 , G11C2207/2263
摘要： Circuit and method of writing a toggle memory (112), in particular an MRAM, according to which a toggle write operation is conditionally aborted in response to data read from the memory (112) so that the memory state is toggled only in case the new data to be written differs from that already contained in the memory (112).
-
公开(公告)号：EP1665277A4
公开(公告)日：2008-01-09
申请号：EP04778154
申请日：2004-07-15
CPC分类号： G11C11/1695 , G11C11/1675
摘要： A write driver (36) uses a reference current (102) that is reflected to a driver circuit (114) by a voltage. The driver circuit (114) is sized in relation to the device (104) that provides the voltage so that the current through the driver (114) is a predetermined multiple of the reference current (102). This voltage is coupled to the driver circuit (114) through a switch (110). The switch (110) is controlled so that the driver circuit (114) only receives the voltage when the write line (52) is to have write current through it as determined by a decoder (22) responsive to an address. The driver (114) is affirmatively disabled when the write line (52) is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled (120) to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.
-
公开(公告)号：EP1671328A4
公开(公告)日：2008-01-02
申请号：EP04783896
申请日：2004-09-14
发明人： GARNI BRADLEY J , ANDRE THOMAS J , NAHAS JOSEPH J
CPC分类号： G11C29/50 , G11C11/16 , G11C2029/5002
摘要： A circuit (30) provides a stress voltage to magnetic tunnel junctions (MTJs) (34-48), which comprise the storage elements of a magnetoresitive random access memory (MRAM) (10), during an accelerated life test of the MRAM (10). The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit (70) is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit (24) that mocks the loading characteristics of the portion of the memory array (12) being stressed. The result is a closely defined voltage applied to the MTJs (34-48) so that the magnitude of the accelaration is well defined for all of the memory cells (34-48).
-
4.发明公开MRAM ARCHITECTURE WITH A GROUNDED WRITE BIT LINE AND ELECTRICALLY ISOLATED READ BIT LINE 有权与相关的写入和电大规模MRAM架构隔离的读出位线
公开(公告)号：EP1588372A4
公开(公告)日：2006-05-10
申请号：EP04702960
申请日：2004-01-16
发明人： NAHAS JOSEPH J
CPC分类号： G11C11/16
摘要： Each memory cell (260, 262, 266, 268) of a magnetoresistive random access memory (MRAM) array (200) has a magnetoresistive tunnel junction (MTJ) and a transistor (261) coupled to the MTJ. Writing occurs by write lines (220, 232) along rows and columns of the array. One set of the write lines (232, 236) is connected to the end of the MTJs that is not connected to the transistors. These write lines are thereby close to the MTJs and thus have good magnetic coupling to the MTJs, which is important in keeping write current low. These write lines are driven on one end by drivers (240, 252). Sensing on the other hand occurs on a read bit line (222) that is coupled to the end of the transistor of the memory cell that is not coupled to the MTJ. By having the sense amplifier(s) (270) on a different line from the write drivers, sensing is not slowed by the capacitance of the write drivers (240, 252).
-
-
-
搜索结果
4 条记录 (耗时 0.008 秒)
