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    METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT
    1.
    发明公开
    METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT 有权
    VERFAHREN UND SYSTEMEFÜRNICHTFLÜCHTIGESPEICHERDATENVERWALTUNG

    公开(公告)号：EP3098814A1

    公开(公告)日：2016-11-30

    申请号：EP16152561.3

    申请日：2016-01-25

    申请人： Winbond Electronics Corp.

    发明人： Lien, Chuen-Der ,  Shieh, Ming-Huei ,  Lin, Chi-shun (Elbert)

    IPC分类号： G11C13/00 ,  G11C7/04 ,  G11C11/00

    CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1072 ,  G11C5/148 ,  G11C7/04 ,  G11C7/20 ,  G11C11/005 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0059 ,  G11C14/0036 ,  G11C14/0045 ,  G11C29/12 ,  G11C29/52

    摘要： A system includes a first resistive nonvolatile memory array, a second transistor-based nonvolatile memory array and a memory controller. The memory controller is configured to write data of the first resistive nonvolatile memory array together with an indicator bit to the second transistor-based nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events and write back the data stored in the second transistor-based nonvolatile memory array to the first resistive nonvolatile memory array when the indicator bit is valid.

    摘要翻译： 系统包括第一电阻性非易失性存储器阵列，第二晶体管非易失性存储器阵列和存储器控制器。 存储器控制器被配置为将第一电阻性非易失性存储器阵列的数据与指示符位一起写入到第二基于晶体管的非易失性存储器阵列，根据系统的高电平确定指示符位是否有效， 温度事件，在高温事件之后的接收命令，预定数量的功率上升，或者在预定数量的高温事件中的每一个之后的加电或接收命令，并将存储在第二晶体管的数据 当指示符位有效时，非易失性存储器阵列到第一电阻性非易失性存储器阵列。

    SCHALTKREISEINHEIT ZUR BEREITSTELLUNG EINES KRYPTOGRAPHISCHEN SCHLÜSSELS UNTER VERWENDUNG VON MEHREREN PUFS
    2.
    发明公开
    SCHALTKREISEINHEIT ZUR BEREITSTELLUNG EINES KRYPTOGRAPHISCHEN SCHLÜSSELS UNTER VERWENDUNG VON MEHREREN PUFS 审中-公开
    电路单元，用于提供加密密钥进行多源的PUF

    公开(公告)号：EP2903201A1

    公开(公告)日：2015-08-05

    申请号：EP14189740.5

    申请日：2014-10-21

    申请人： Siemens Aktiengesellschaft

    发明人： Falk, Rainer

    IPC分类号： H04L9/08 ,  G09C1/00

    CPC分类号： H04L9/3278 ,  G09C1/00 ,  G11C11/1695 ,  H04L9/0816 ,  H04L9/0866 ,  H04L2209/12 ,  H04L2209/24

    摘要： Es wird eine Schaltkreiseinheit (1) zur Bereitstellung eines kryptographischen Schlüssels vorgeschlagen. Die Schaltkreiseinheit (1) weist eine Physical Unclonable Function (11) zum Erzeugen eines Response-Wertes (RI) in Antwort auf einen Challenge-Wert (CI), eine Bestimmungseinheit (12) zum Bestimmen einer Mehrzahl von Challenge-Werten (CI) und zum Eingeben der Mehrzahl von Challenge-Werten (CI) in die Physical Unclonable Function (11), um eine Mehrzahl von Response-Werten (RI) zu erzeugen, eine Vergleichseinheit (13) zum Bereitstellen eines Vergleichsergebnisses durch Vergleichen der erzeugten Mehrzahl von Response-Werten (RI) mit einem vordefinierten Referenzwert (18), und eine Bereitstellungeinheit (14) zum Bereitstellen eines der Mehrzahl von Challenge-Werten (CI) als kryptographischen Schlüssel (KS) basierend auf dem bereitgestellten Vergleichsergebnis auf.
    Mit der vorgeschlagenen Schaltkreiseinheit werden Challenge-Werte nicht vorgegeben und dazu passende Response-Werte ermittelt, sondern ein Challenge-Wert gesucht, der am besten zu einem vorgegebenen Referenzwert passt. Dieser wird dann als kryptographischer Schlüssel verwendet. Daher ist es nicht erforderlich, den kryptographischen Schlüssel zu erzeugen und dann geschützt zu speichern.
    Des Weiteren wird ein Verfahren zur Bereitstellung eines kryptographischen Schlüssels vorgeschlagen.

    摘要翻译： 它提出了一种电路单元（1），用于提供加密密钥。 的电路单元（1）包括物理不可克隆功能块（11），用于响应于询问值（CI），一个确定单元（12），用于确定多个挑战值（CI）产生的响应值（RI）和 在物理不可克隆功能块输入所述多个挑战值（CI）的（11），以产生多个响应值的（RI），比较单元（13），用于通过比较由响应生成的多个提供的比较结果 值（RI）与预定的基准值（18），以及用于提供多个挑战值（CI）的基于设置在比较结果的密码密钥（KS）提供单元（14）。 所提出的电路单元的挑战值挑战值不规定，并确定适当的响应值，但寻求最预定的参考值相匹配。 这则用作加密密钥。 因此，没有必要生成加密密钥，然后存储保护。 还建议提供一个加密密钥的方法。

    STRESSED MAGNETORESISTIVE TAMPER DETECTION DEVICES
    3.
    发明公开
    STRESSED MAGNETORESISTIVE TAMPER DETECTION DEVICES 有权
    回弹磁阻伪造检测装置

    公开(公告)号：EP2135254A1

    公开(公告)日：2009-12-23

    申请号：EP08742038.6

    申请日：2008-03-10

    申请人： NVE Corporation

    发明人： DEAK, James, G.

    IPC分类号： G11C19/08

    CPC分类号： G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1695

    摘要： A tamper sensing system mounted with respect to a protected structure so as to have corresponding stress changes occur therein in response to selected kinds of tamperings with said protected structure comprising a first pair of stress affected magnetoresistive memory devices each capable of having a magnetic material layer therein established in a selected one of a pair of alternative magnetization states if in a first kind of stress condition and of being established in a single magnetization state if in an alternative second kind of stress condition, and the magnetic material layer in each having a magnetization in a first direction in one of the pair of alternative magnetization states and in a second direction in that remaining one of the pair of magnetization states. A first magnetizing electrical conductor extends adjacent to each of the first pair of stress affected magnetoresistive memory devices to establish said magnetic material layer in that one of said pair of alternative magnetization states thereof so as to have its said corresponding magnetization be oppositely directed with respect to said magnetization of that other. The first pair of stress affected magnetoresistive memory devices can each be provided by a spin dependent tunneling device having differing numbers of magnetization states available thereto depending on whether being in differing ones of alternative stress conditions.

    INTEGRITY CONTROL FOR DATA STORED IN A NON-VOLATILE MEMORY
    4.
    发明授权
    INTEGRITY CONTROL FOR DATA STORED IN A NON-VOLATILE MEMORY 有权
    完整性控制在非挥发性存储器中存储的数据

    公开(公告)号：EP1634299B1

    公开(公告)日：2009-04-01

    申请号：EP04744341.1

    申请日：2004-05-26

    申请人： NXP B.V.

    发明人： JOCHEMSEN, Robert ,  LAMBERT, Nicolaas ,  FONTIJN, Wilhelmus, F., J. ,  DENISSEN, Adrianus, J., M.

    IPC分类号： G11C11/16

    CPC分类号： G06F11/1068 ,  G11C11/1675 ,  G11C11/1695 ,  G11C29/08 ,  G11C2029/4402

    摘要： The present invention relates to a write controller (10) for a memory with a plurality of non-volatile storage cells, a read controller for a memory with a plurality of non­volatile storage cells, to a combined write/read controller, to a solid state device comprising a memory with a plurality of non-volatile storage cells, a programmer device for writing a binary code to a non-volatile memory, to a method for writing data comprising at least one input bit to a memory having non-volatile storage cells, and to a method for controlling the integrity of data comprising at least one input bit stored in non-volatile storage cells of a memory. The invention provides a reliable detection of changes that have occurred to the content of a non-volatile memory. The basic concept of the present invention is to extend information stored in a non-volatile memory by at least one checking bit. The checking bit is allocated to one code bit, or to each of a plurality of code bits. The allocation is preferably reflected in an allocation of memory cells storing the input and code bits.

    WRITE DRIVER FOR A MAGNETORESISTIVE MEMORY
    6.
    发明公开
    WRITE DRIVER FOR A MAGNETORESISTIVE MEMORY 审中-公开
    写驱动器FOR A磁阻存储器

    公开(公告)号：EP1665277A4

    公开(公告)日：2008-01-09

    申请号：EP04778154

    申请日：2004-07-15

    申请人： FREESCALE SEMICONDUCTOR INC

    发明人： NAHAS JOSEPH J ,  ANDRE THOMAS W ,  SUBRAMANIAN CHITRA K ,  LIN HALBERT

    IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16

    CPC分类号： G11C11/1695 ,  G11C11/1675

    摘要： A write driver (36) uses a reference current (102) that is reflected to a driver circuit (114) by a voltage. The driver circuit (114) is sized in relation to the device (104) that provides the voltage so that the current through the driver (114) is a predetermined multiple of the reference current (102). This voltage is coupled to the driver circuit (114) through a switch (110). The switch (110) is controlled so that the driver circuit (114) only receives the voltage when the write line (52) is to have write current through it as determined by a decoder (22) responsive to an address. The driver (114) is affirmatively disabled when the write line (52) is intended to not have current passing through it. As an enhancement to overcome ground bounce due to high currents, the input to the driver can be capacitively coupled (120) to the ground terminal that experiences such bounce. Additional enhancements provide benefits in amplitude and edge rate control.