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公开(公告)号:EP0147138A3
公开(公告)日:1986-02-19
申请号:EP84308709
申请日:1984-12-13
CPC分类号: H04N7/0132 , H04N5/915 , Y10S348/91
摘要: In a field signal-frame signal conversion system including means for applying a'delayed field signal.(18) delayed by one half of a horizontal scanning period and a direct field signa) (17), which is the same as the delayed field signal (18) but not delayed, and switching means (16) for alternately selecting the field signals at a time interval of one vertical scanning period to provide a frame signal, a circuit for preventing appearance of flicker attributable to the field signal - frame signal conversion, the circuit comprising a synchronizing signal separating means (50) separating a synchronizing signal from the frame signal appearing at the output of the switching means (16), a sampling pulse generating means (52) generating, in response to the application of the separated synchronizing signal, a sampling pulse signal synchronous with the change points from the sync tip level to the pedestal level and having a pulse width equal to or smaller than that of the serrating pulses, a sample and hold means (53) operating in response to the sampling pulse signal for sampling the frame signal appearing at the output of the switching means (16), a clamping voltage generating means (54) comparing the output signal of the sample and hold means (53) with a reference value and generating a voltage signal proportional to the difference therebetween, and two clamping circuits (34, 33) connected to the direct and delayed field signal lines (17,18) respectively and controlled by the output signal of the clamping voltage generating means (54) for maintaining constant the pedestal level of the direct and delayed field signals.