利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.012 秒)

    Semiconductor memory device with an increased band width
    1.
    发明公开
    Semiconductor memory device with an increased band width 失效
    Halbleiterspeicheranordnung miterhöhterBandbreite

    公开(公告)号：EP0829880A2

    公开(公告)日：1998-03-18

    申请号：EP97301157.0

    申请日：1997-02-21

    申请人： FUJITSU LIMITED

    发明人： Tsuboi, Hironobu ,  Okajima, Yoshinori ,  Higuchi, Tsuyoshi ,  Koga, Makoto

    IPC分类号： G11C5/02 ,  G11C11/409

    CPC分类号： G11C5/025 ,  G11C7/10 ,  G11C11/409

    摘要： A semiconductor memory device includes a plurality of bit lines (BL0 through BL7 and /BL0 through /BL7), first sense amplifiers (60) each connected to a corresponding one of the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7), and a first data bus (24) laid out in parallel to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7) and connected to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7) via gates and the first sense amplifiers (60). The semiconductor memory device further includes column-selection lines (22) laid out perpendicularly to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7) to open at least one of the gates to connect the first data bus (24) to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7).

    摘要翻译： 半导体存储器件包括多个位线（BL0至BL7和/ BL0至/ BL7），第一读出放大器（60）分别连接到多条位线（BL0至BL7和/ BL0至/ BL7）中的相应一条位线 ）和与多个位线（BL0〜BL7和/ BL0〜BL7）并联布置并连接到多个位线（BL0〜BL7和/ BL0〜BL7）的第一数据总线（24） 通过栅极和第一读出放大器（60）。 半导体存储器件还包括垂直于多条位线（BL0至BL7和/ BL0至/ BL7）布置的列选择线（22），以打开至少一个栅极以连接第一数据总线（24） 到多个位线（BL0〜BL7，/ BL0〜BL7）。

    Semiconductor memory device with an increased band width
    2.
    发明公开
    Semiconductor memory device with an increased band width 失效
    具有增加的带宽的半导体存储器件

    公开(公告)号：EP0829880A3

    公开(公告)日：1999-05-12

    申请号：EP97301157.0

    申请日：1997-02-21

    申请人： FUJITSU LIMITED

    发明人： Tsuboi, Hironobu ,  Okajima, Yoshinori ,  Higuchi, Tsuyoshi ,  Koga, Makoto

    IPC分类号： G11C5/02 ,  G11C11/409

    CPC分类号： G11C5/025 ,  G11C7/10 ,  G11C11/409

    摘要： A semiconductor memory device includes a plurality of bit lines (BL0 through BL7 and /BL0 through /BL7), first sense amplifiers (60) each connected to a corresponding one of the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7), and a first data bus (24) laid out in parallel to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7) and connected to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7) via gates and the first sense amplifiers (60). The semiconductor memory device further includes column-selection lines (22) laid out perpendicularly to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7) to open at least one of the gates to connect the first data bus (24) to the plurality of bit lines (BL0 through BL7 and /BL0 through /BL7).

    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
    6.
    发明公开
    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation 失效
    带有输入/输出接口的半导体集成电路，适用于小幅度工作

    公开(公告)号：EP0883248A2

    公开(公告)日：1998-12-09

    申请号：EP98114376.1

    申请日：1993-06-14

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao ,  Eto, Satoshi ,  Takemae, Yoshihiro ,  Koga, Makoto ,  Yoshioka, Hiroshi

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018585

    摘要： An input circuit is described for accepting different types of input signals.
    An instruction means (14,86) selects a first mode when an input reference signal is given, and a second mode when it is not. In the first mode, the input voltage is compared with the input reference signal, whereas in the second mode the threshold is a predetermined threshold.

    摘要翻译： 描述了用于接受不同类型的输入信号的输入电路。 指令装置（14,86）在给出输入参考信号时选择第一模式，当给出输入参考信号时选择第二模式。 在第一模式中，将输入电压与输入参考信号进行比较，而在第二模式中，阈值是预定阈值。

    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
    8.
    发明公开
    Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation 失效
    适用于低振幅的半导体集成电路具有输入/输出接口

    公开(公告)号：EP0883247A3

    公开(公告)日：1999-07-21

    申请号：EP98114375.3

    申请日：1993-06-14

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao ,  Eto, Satoshi ,  Takemae, Yoshihiro ,  Koga, Makoto ,  Yoshioka, Hiroshi

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018585

    摘要： The circuit of the invention has a PMOS (55) and NMOS (56) transistor with an output terminal arranged between them. They operate as a push-pull circuit. There is further provided a means for cutting of the PMOS transistor provided (46,47) in response to a predetermined level destination signal.

    摘要翻译： 输入电路被描述用于接受不同类型的输入信号的。 的指令装置（86）选择第一模式，当输入参考信号（VREF1）给出，和第二模式当不是。 在第一模式中，输入电压与所述参考输入信号相比较，而在第二模式中的阈值是一个预定阈值。