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    Logic circuit
    1.
    发明公开
    Logic circuit 失效
    逻辑电路

    公开(公告)号：EP0341732A2

    公开(公告)日：1989-11-15

    申请号：EP89108588.8

    申请日：1989-05-12

    申请人： FUJITSU LIMITED

    发明人： Shimotsuhama, Isao c/o FUJITSU LIMITED ,  Emori, Shinji c/o FUJITSU LIMITED ,  Watanabe, Yoshio c/o FUJITSU LIMITED ,  Tamamura, Masaya c/o FUJITSU LIMITED

    IPC分类号： H03K19/086

    CPC分类号： H03K19/086 ,  H03K19/09436

    摘要： A logic circuit having a differential amplifier comprising a transistor pair of first (T₁) and second (T₂) transistors and further comprising a third transistor (T₃) connected in parallel with the second transistor (T₂), a first driving circuit (1) operatively connected to drive the first and second transistors with complementary output signals (A, A ) having a first (H₁) and second (L₁) levels, and a second driving circuit (2) operatively connected to drive the third transistor (T₃) with an output signal (B) having third (H₂) and fourth (L₂) levels, one (H₂) of which third and fourth levels is beyond one end of the range between the first and second levels and the other (L₂) of which levels is either within that range or beyond the other end of that range.

    摘要翻译： 一种具有差分放大器的逻辑电路，该差分放大器包括第一（T 1）和第二（T 2）晶体管的晶体管对，还包括与第二晶体管（T 2）并联的第三晶体管（T 3），第一驱动电路（1） （A，A）和第二驱动电路（2）驱动第一和第二晶体管，第二驱动电路（2）可操作地连接以驱动第三晶体管（T 3），第一和第二晶体管具有第一（H 1）和第二 （H 2）和第四（L 2）电平的输出信号（B），其中第三和第四电平的一个（H 2）超出第一和第二电平之间的范围的一端，而另一个电平（L 2） 在该范围内或超出该范围的另一端。

    Logic circuit
    3.
    发明公开
    Logic circuit 失效
    逻辑电路

    公开(公告)号：EP0341732A3

    公开(公告)日：1990-04-25

    申请号：EP89108588.8

    申请日：1989-05-12

    申请人： FUJITSU LIMITED

    发明人： Shimotsuhama, Isao c/o FUJITSU LIMITED ,  Emori, Shinji c/o FUJITSU LIMITED ,  Watanabe, Yoshio c/o FUJITSU LIMITED ,  Tamamura, Masaya c/o FUJITSU LIMITED

    IPC分类号： H03K19/086

    CPC分类号： H03K19/086 ,  H03K19/09436

    摘要： A logic circuit having a differential amplifier comprising a transistor pair of first (T₁) and second (T₂) transistors and further comprising a third transistor (T₃) connected in parallel with the second transistor (T₂), a first driving circuit (1) operatively connected to drive the first and second transistors with complementary output signals (A, A ) having a first (H₁) and second (L₁) levels, and a second driving circuit (2) operatively connected to drive the third transistor (T₃) with an output signal (B) having third (H₂) and fourth (L₂) levels, one (H₂) of which third and fourth levels is beyond one end of the range between the first and second levels and the other (L₂) of which levels is either within that range or beyond the other end of that range.