公开(公告)号：EP0351779B1

公开(公告)日：1994-11-09

申请号：EP89113155.9

申请日：1989-07-18

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Fujimoto, Nobuhiro ,  Ishihara, Tomohiro ,  Wakisaka, Takaaki

IPC: H04L7/033 ,  H04L7/02

CPC classification number: H04L7/0012 ,  H04L7/0045 ,  H04L7/005

公开(公告)号：EP0409230A3

公开(公告)日：1991-10-30

申请号：EP90113855.2

申请日：1990-07-19

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Yamashita, Haruo ,  Ishihara, Tomohiro ,  Wakisaka, Takaaki

IPC: H04J3/06 ,  H04L7/02

CPC classification number: H04J3/0626 ,  H04L7/005

Abstract: A phase matching circuit for realizing accurate data transmission and reception through phase shift control only during a data invalid region. The phase matching circuit includes an input buffer (210) for taking first data with a first clock; an output buffer (218) sending second data with a second clock: a phase detector (220) for comparing the phases of first and second clocks and detecting a phase difference within a predetermined value; a phase control unit (216) for directly outputting the first data to the output buffer when the phase difference within the predetermined value is not detected or for outputting the first data phase shifted to the output buffer, and for converting the first data synchronized with the first clock to the second data of the same content as the first data synchronized with the second clock in the same frequency as the first clock: an invalid data region detector (214) for detecting an invalid region of first data; and a phase shifter controller (212) for inhibiting phase shift control in the phase control unit (216) when the invalid data region detector does not detect the invalid region and for allowing phase shift control in the phase control unit when the invalid data region detector detects the invalid region.

公开(公告)号：EP1227609A3

公开(公告)日：2005-09-28

申请号：EP01116746.7

申请日：2001-07-19

Applicant: FUJITSU LIMITED

Inventor： Takagi, Yoshinobu ,  Morita, Hirotaka ,  Komatsu, Chiyoko ,  Miyashita, Takuya ,  Taniguchi, Atsuki

IPC: H04J3/24 ,  H04Q11/04

CPC classification number: H04Q11/04 ,  H04J3/247 ,  H04Q2213/13036 ,  H04Q2213/13103 ,  H04Q2213/13292

Abstract: A transmission apparatus includes an input port part having a plurality of input ports, an output window part having a plurality of buffers, a switch part making connections between the plurality of input ports and the plurality of buffers, a selection control circuit controlling the switch part so that data from the plurality of input ports are stored in buffers that have available areas among the plurality of buffers in accordance with data storage states of the plurality of buffers, and a time division multiplexing part multiplexing the data read from the plurality of buffers in time division multiplexing for transmission.

公开(公告)号：EP0351779A3

公开(公告)日：1991-12-18

申请号：EP89113155.9

申请日：1989-07-18

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Fujimoto, Nobuhiro ,  Ishihara, Tomohiro ,  Wakisaka, Takaaki

IPC: H04L7/033 ,  H04L7/02

CPC classification number: H04L7/0012 ,  H04L7/0045 ,  H04L7/005

Abstract: A phase adjusting circuit for adjusting a phase of each bit of serial data (D1) by synchronizing with a system clock (CK2), comprising a plurality of registers (31, 32, 33, 34); inputting each bit of the data into a corresponding one of the plurality of registers (31, 32, 33, 34) in a predetermined cyclic order, synchronized with a receiving clock (CK1) which is extracted from the data, and outputting outputs of the registers (31, 32, 33, 34) in parallel. The outputs are each selected in a selector circuit (44) under a control of the selector control signal in the same order as the above input into the registers (31, 32, 33, 34). The selector control signal is generated by detecting a phase relationship between phases of the receiving clock (CK1) and the system clock (CK2), and generating a selector control signal having phase which is determined according to the phase relationship. Then, each bit of the above selected output is synchronized with the system clock (CK2).

公开(公告)号：EP1037421A3

公开(公告)日：2002-10-16

申请号：EP99309423.4

申请日：1999-11-25

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki

IPC: H04J3/16

CPC classification number: H04J3/076 ,  H04J3/1611 ,  Y10S370/907

Abstract: In a transmission method and apparatus, low-speed SDH signals are multiplexed into a high-speed SDH frame, the high-speed SDH frame including at least an information payload, a line overhead and a section overhead, the section overhead being divided into a first section overhead SOH and a second section overhead SOH, the first SOH carrying regenerator SOH bytes and the second SOH carrying multiplex SOH bytes. The multiplex SOH bytes in the second SOH of the high-speed SDH frame are detected without changing the line overhead and the payload when the high-speed SDH frame reaches a receive-side high-level line terminating equipment. The multiplex SOH bytes in the second SOH of the high-speed SDH frame are generated without changing the line overhead and the payload before the high-speed SDH frame is transmitted by a transmit-side high-level line terminating equipment.

公开(公告)号：EP0409230B1

公开(公告)日：1995-09-27

申请号：EP90113855.2

申请日：1990-07-19

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Yamashita, Haruo ,  Ishihara, Tomohiro ,  Wakisaka, Takaaki

IPC: H04J3/06 ,  H04L7/02

CPC classification number: H04J3/0626 ,  H04L7/005

公开(公告)号：EP0372458A2

公开(公告)日：1990-06-13

申请号：EP89122339.8

申请日：1989-12-04

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Yamashita, Haruo Dai-2 Iizuka-haitsu 101 ,  Ishihara, Tomohiro ,  Wakisaka, Takaaki

IPC: H04J3/07

CPC classification number: H04J3/0623

Abstract: A reception processing unit (21) which receives digital data with data frame consisting of pairs of supervisory data fields and information data filed and further including the data frames negative stuffs or positive stuffs in accordance with need and discovers the head position of the information data filed, wherein an enable signal is produced only at the timing where the information data filed should appear in the successive data frames received; a count operation of a counter (32) is performed only in the term when the enable signal is being generated; and the head position is detected each time the counter finishes counting a number of bytes equal to the fixed length of the information data.

Abstract translation: 一种接收处理单元，用于根据需要接收数字数据，该数据数据由包含监视数据字段和信息数据对的组成的数据帧组成，并且还根据需要进一步包括数据帧负数或正数，并且发现信息数据段的头部位置 其中，只有在所接收的连续数据帧中出现信息数据的定时才产生使能信号; 计数器（32）的计数操作仅在产生使能信号的术语中执行; 并且每当计数器完成计数等于信息数据的固定长度的字节数时，检测头位置。

公开(公告)号：EP0305992B1

公开(公告)日：1994-08-17

申请号：EP88114191.5

申请日：1988-08-31

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Ohtsuka, Tomoyuki ,  Naitou, Hidetoshi ,  Kondo, Ryuichi

IPC: H04J3/08 ,  H04J3/04

CPC classification number: H04J3/08

公开(公告)号：EP0372458A3

公开(公告)日：1991-07-24

申请号：EP89122339.8

申请日：1989-12-04

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Yamashita, Haruo Dai-2 Iizuka-haitsu 101 ,  Ishihara, Tomohiro ,  Wakisaka, Takaaki

IPC: H04J3/07

CPC classification number: H04J3/0623

Abstract: A reception processing unit (21) which receives digital data with data frame consisting of pairs of supervisory data fields and information data filed and further including the data frames negative stuffs or positive stuffs in accordance with need and discovers the head position of the information data filed, wherein an enable signal is produced only at the timing where the information data filed should appear in the successive data frames received; a count operation of a counter (32) is performed only in the term when the enable signal is being generated; and the head position is detected each time the counter finishes counting a number of bytes equal to the fixed length of the information data.

公开(公告)号：EP0409230A2

公开(公告)日：1991-01-23

申请号：EP90113855.2

申请日：1990-07-19

Applicant: FUJITSU LIMITED

Inventor： Taniguchi, Atsuki ,  Yamashita, Haruo ,  Ishihara, Tomohiro ,  Wakisaka, Takaaki

IPC: H04J3/06 ,  H04L7/02

CPC classification number: H04J3/0626 ,  H04L7/005

Abstract: A phase matching circuit for realizing accurate data transmission and reception through phase shift control only during a data invalid region. The phase matching circuit includes an input buffer (210) for taking first data with a first clock; an output buffer (218) sending second data with a second clock: a phase detector (220) for comparing the phases of first and second clocks and detecting a phase difference within a predetermined value; a phase control unit (216) for directly outputting the first data to the output buffer when the phase difference within the predetermined value is not detected or for outputting the first data phase shifted to the output buffer, and for converting the first data synchronized with the first clock to the second data of the same content as the first data synchronized with the second clock in the same frequency as the first clock: an invalid data region detector (214) for detecting an invalid region of first data; and a phase shifter controller (212) for inhibiting phase shift control in the phase control unit (216) when the invalid data region detector does not detect the invalid region and for allowing phase shift control in the phase control unit when the invalid data region detector detects the invalid region.

Abstract translation: 一种相位匹配电路，用于仅在数据无效区域中通过相移控制实现精确的数据发送和接收。 相位匹配电路包括用于以第一时钟采集第一数据的输入缓冲器（210） 输出缓冲器（218），用第二时钟发送第二数据：相位检测器（220），用于比较第一和第二时钟的相位并检测预定值内的相位差; 相位控制单元（216），用于当未检测到预定值内的相位差时直接将第一数据输出到输出缓冲器，或者用于输出偏移到输出缓冲器的第一数据相位，并且用于将与第 第一时钟到与第一时钟同步的与第一时钟同步的第一数据的第二数据的第二数据与第一时钟相同的频率：用于检测第一数据的无效区域的无效数据区域检测器（214） 以及用于当无效数据区域检测器没有检测到无效区域时禁止相位控制单元（216）中的相移控制的移相器控制器（212），并且当无效数据区域检测器 检测无效区域。