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    Variable delay circuit
    2.
    发明公开
    Variable delay circuit 失效
    可变延迟电路

    公开(公告)号：EP0536689A1

    公开(公告)日：1993-04-14

    申请号：EP92117027.0

    申请日：1992-10-06

    申请人： FUJITSU LIMITED

    发明人： Koyashiki, Tsuyoshi, c/o FUJITSU LIMITED ,  Teruyama, Kohei

    IPC分类号： H03K5/13

    CPC分类号： H03K5/133 ,  H03K5/131 ,  H03K2005/00065 ,  H03K2005/00195

    摘要： A variable delay circuit includes a first power source line (140, 12, 25, 42, 60) for supplying a first power source voltage (V DD ), a second power source line (143, 13, 26, 43, 61) for supplying a second power source voltage (V SS ) which is smaller than the first power source voltage, an input terminal (145, 9, 22, 37, 57) for receiving an input signal (IN), a selection terminal (148, 10, 23, 38-40, 58) for receiving a selection signal (S, S₁-S₃), an output terminal (141, 11, 24, 41, 59) for outputting an output signal (OUT) which is delayed relative to the input signal, a pull-up circuit (142) coupled between the first power source line and the output terminal for carrying out a pull-up operation based on the input signal which is received via the input terminal, and a pull-down circuit (144) coupled between the output terminal and the second power source line for carrying out a pull-down operation based on the input signal which is received via the input terminal. The pull-up or pull-down circuit has a delay time which is variable in response to the selection signal which is received via the selection terminal.

    摘要翻译： 一种可变延迟电路，包括用于提供第一电源电压（VDD）的第一电源线（140,12,25,42,60），用于提供第一电源电压（VDD）的第二电源线（143,13,24,43,61） 一个比第一电源电压小的第二电源电压（VSS），一个用于接收输入信号（IN）的输入端（145,9,22,37,57），一个选择端（148,10,23 ，用于接收一个选择信号（S，S 1 -S 3）的输出端（141，11,24,41,59），用于输出一个相对于输入信号延迟的输出信号（OUT）的输出端 ，耦合在第一电源线和输出端之间的上拉电路（142），以及下拉电路（144），用于基于经由输入端接收的输入信号来执行上拉操作， 耦合在输出端和第二电源线之间，用于根据经输入端接收的输入信号执行下拉操作。 上拉或下拉电路具有响应于经由选择端子接收的选择信号而可变的延迟时间。