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公开(公告)号：EP0362050A2
公开(公告)日：1990-04-04
申请号：EP89402634.3
申请日：1989-09-26
发明人： Masuyama, Masaru , Takemae, Yoshihiro , Endoh, Tetsuhiko , Komyoji, Hirosuke , Tanaka, Ryuji , Itakura, Katsuhiko
CPC分类号： G06K19/07 , G06K7/0008
摘要： A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal (5, 21, 62a, 62b), a memory part (1, 12, 13, M0-M7) having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal (2, 16, 70) for receiving an address signal, a first input terminal (7, 19, 66) for receiving a first chip select signal which selects a first byte, a second input terminal (8, 20, 65) for receiving a second chip select signal which selects a second byte, and a decoder circuit (9, 15, 61) for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.
摘要翻译： 在具有任意位宽的数据总线的卡写入和/或读取装置中使用存储卡，并向存储卡写入和/或读取数据。 存储卡包括数据输入/输出端子（5,21,62a，62b），具有数据总线的存储器部分（1,12,13，M0-M7），其位宽至少为n位，用于耦合到 经由数据输入/输出端子的卡写入和/或读取装置的数据总线，用于接收地址信号的地址输入端子（2,16，70），用于接收地址信号的第一输入端子（7，19,66） 选择第一字节的第一芯片选择信号，用于接收选择第二字节的第二芯片选择信号的第二输入端子（8,20,65）以及用于确定位的解码器电路（9,15,61） 基于第一和第二芯片选择信号以及一个或多个任意的芯片选择信号，用于卡写入和/或读取装置之间的数据通信的存储器部分的数据总线的宽度与n位和n / N位之一 通过向存储器部分提供控制信号，其中n，N和n / N是正整数的地址信号的位。
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公开(公告)号：EP0362050A3
公开(公告)日：1991-04-03
申请号：EP89402634.3
申请日：1989-09-26
发明人： Masuyama, Masaru , Takemae, Yoshihiro , Endoh, Tetsuhiko , Komyoji, Hirosuke , Tanaka, Ryuji , Itakura, Katsuhiko
CPC分类号： G06K19/07 , G06K7/0008
摘要： A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal (5, 21, 62a, 62b), a memory part (1, 12, 13, M0-M7) having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal (2, 16, 70) for receiving an address signal, a first input terminal (7, 19, 66) for receiving a first chip select signal which selects a first byte, a second input terminal (8, 20, 65) for receiving a second chip select signal which selects a second byte, and a decoder circuit (9, 15, 61) for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.
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公开(公告)号：EP0362050B1
公开(公告)日：1994-11-17
申请号：EP89402634.3
申请日：1989-09-26
发明人： Masuyama, Masaru , Takemae, Yoshihiro , Endoh, Tetsuhiko , Komyoji, Hirosuke , Tanaka, Ryuji , Itakura, Katsuhiko
CPC分类号： G06K19/07 , G06K7/0008
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