利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

232 条记录 (耗时 0.015 秒)

    Memory card
    2.
    发明公开
    Memory card 失效
    Speicherkarte。

    公开(公告)号：EP0362050A2

    公开(公告)日：1990-04-04

    申请号：EP89402634.3

    申请日：1989-09-26

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Masuyama, Masaru ,  Takemae, Yoshihiro ,  Endoh, Tetsuhiko ,  Komyoji, Hirosuke ,  Tanaka, Ryuji ,  Itakura, Katsuhiko

    IPC分类号： G06K19/07 ,  G06K7/00

    CPC分类号： G06K19/07 ,  G06K7/0008

    摘要： A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal (5, 21, 62a, 62b), a memory part (1, 12, 13, M0-M7) having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal (2, 16, 70) for receiving an address signal, a first input terminal (7, 19, 66) for receiving a first chip select signal which selects a first byte, a second input terminal (8, 20, 65) for receiving a second chip select signal which selects a second byte, and a decoder circuit (9, 15, 61) for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.

    摘要翻译： 在具有任意位宽的数据总线的卡写入和/或读取装置中使用存储卡，并向存储卡写入和/或读取数据。 存储卡包括数据输入/输出端子（5,21,62a，62b），具有数据总线的存储器部分（1,12,13，M0-M7），其位宽至少为n位，用于耦合到 经由数据输入/输出端子的卡写入和/或读取装置的数据总线，用于接收地址信号的地址输入端子（2,16，70），用于接收地址信号的第一输入端子（7，19,66） 选择第一字节的第一芯片选择信号，用于接收选择第二字节的第二芯片选择信号的第二输入端子（8,20,65）以及用于确定位的解码器电路（9,15,61） 基于第一和第二芯片选择信号以及一个或多个任意的芯片选择信号，用于卡写入和/或读取装置之间的数据通信的存储器部分的数据总线的宽度与n位和n / N位之一 通过向存储器部分提供控制信号，其中n，N和n / N是正整数的地址信号的位。

    Semiconductor memory device having means for replacing defective memory cells
    4.
    发明公开
    Semiconductor memory device having means for replacing defective memory cells 失效
    具有用于替换有缺陷的记忆细胞的手段的半导体存储器件

    公开(公告)号：EP0383452A3

    公开(公告)日：1992-12-23

    申请号：EP90300935.5

    申请日：1990-01-30

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

    IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

    CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

    摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

    Memory card
    5.
    发明公开
    Memory card 失效
    存储卡

    公开(公告)号：EP0362050A3

    公开(公告)日：1991-04-03

    申请号：EP89402634.3

    申请日：1989-09-26

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Masuyama, Masaru ,  Takemae, Yoshihiro ,  Endoh, Tetsuhiko ,  Komyoji, Hirosuke ,  Tanaka, Ryuji ,  Itakura, Katsuhiko

    IPC分类号： G06K19/07 ,  G06K7/00

    CPC分类号： G06K19/07 ,  G06K7/0008

    摘要： A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal (5, 21, 62a, 62b), a memory part (1, 12, 13, M0-M7) having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal (2, 16, 70) for receiving an address signal, a first input terminal (7, 19, 66) for receiving a first chip select signal which selects a first byte, a second input terminal (8, 20, 65) for receiving a second chip select signal which selects a second byte, and a decoder circuit (9, 15, 61) for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.

    Semiconductor memory device having serial data input and output circuit
    6.
    发明公开
    Semiconductor memory device having serial data input and output circuit 失效
    具有串行数据输入和输出电路的半导体存储器件

    公开(公告)号：EP0188134A3

    公开(公告)日：1988-08-10

    申请号：EP85309562

    申请日：1985-12-31

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Noguchi, Masaaki FUJITSU Seto-ryo 201 ,  Ogawa, Junji ,  Takemae, Yoshihiro

    IPC分类号： G11C07/00

    CPC分类号： G11C7/1075

    摘要： A dual-port type semiconductor memory device having a serial data input and output circuit (200) provided outside of a memory cell array (1) and operable for high-speed serial data input and output of data in addition to random data access. The semiconductor memory device includes a single decoding circuit (5) triggering at least one gate for transferring data to be stored into or read from the memory cell array in a random data access mode and setting a single bit to a corresponding shift register (24) in the serial data input and output circuit in a serial data input and output operation mode. Preferably, the decoding circuit is operated only during a time for operatively connecting bit lines and latch circuits in the serial data input and output circuit in the serial data input and output operation mode. The serial data input and output circuit is operable independently from the memory cell array, except during the time for operatively connecting the bit lines and the latch circuits through transfer gates, for serially inputting data to or outputting data from the latch circuits through serial data bus by sequentially triggering the serial gates from a certain gate designated by the corresponding shift register in response to the decoding circuit.

    Semiconductor memory device having means for replacing defective memory cells
    8.
    发明公开
    Semiconductor memory device having means for replacing defective memory cells 失效
    一种半导体存储器，包括装置，用于替换有缺陷的存储单元。

    公开(公告)号：EP0383452A2

    公开(公告)日：1990-08-22

    申请号：EP90300935.5

    申请日：1990-01-30

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Kasa, Yasushi ,  Takemae, Yoshihiro ,  Nagasawa, Masanori ,  Arayama, Yuji ,  Terui, Akira ,  Araki, Sunao

    IPC分类号： G06F11/20 ,  G11C11/407 ,  G11C17/16

    CPC分类号： G11C29/76 ,  G06F11/006 ,  G11C11/005 ,  G11C11/407 ,  G11C17/16 ,  G11C29/822

    摘要： A semiconductor memory device comprises a first memory (16, 70, 201-208, 321, 420, 501) comprising memory cells for prestoring fixed data, a decoder (14, 15, 71, 72, 209-216, 225-228, 302, 305, 505, 506) for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory (23, 82, 235, 322, 331, 411, 502, 503) for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part (13, 75, 76, 96, 308, 309, 426, 522, 523, 531) including a third memory (63, 64, 73, 74, 93, 94, 95, 307, 423, 504) for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part (25, 80, 305, 309, 426, 506) supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

    摘要翻译： 一种半导体存储器件包括包含用于的Presto环固定数据存储器单元的第一存储器（16，70，201-208，321，420，501），解码器（14，15，71，72，209-216，225-228， 302，305，505，506），用于输入地址的解码和用于从基于经解码的输入地址，第二存储器（23，82，235，322，331，411，502，503中的第一存储器中读出的固定数据 ），用于存储与在所述第一存储器中，有缺陷的存储单元并预先存储一个数据，其中所述第二存储器包括可编程非易失性存储器单元，判别部（13，75，76，96，308，309，426，522 ，523，531）包括用于识别存储在第一存储器中的每个有缺陷的存储单元的冗余地址的第三存储器（63，64，73，74，93，94，95，307，423，504）是否将 输入地址与所述冗余地址和用于输出铃声当输入地址与所述冗余地址，和一个选择部分（25，80，305，309重合一致的识别信号， 426，506）提供数据从所述第一存储器和第二存储器中读出用于正常地输出婷将数据从第一存储器和选择性地输出婷从第二存储器当从判别部所接收的识别信号中读出的数据。

    Semiconductor memory device having serial data input and output circuit
    9.
    发明公开
    Semiconductor memory device having serial data input and output circuit 失效
    具有串行数据输入和-ausgangsschaltung的半导体存储器件。

    公开(公告)号：EP0188134A2

    公开(公告)日：1986-07-23

    申请号：EP85309562.8

    申请日：1985-12-31

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Noguchi, Masaaki FUJITSU Seto-ryo 201 ,  Ogawa, Junji ,  Takemae, Yoshihiro

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1075

    摘要： A dual-port type semiconductor memory device having a serial data input and output circuit (200) provided outside of a memory cell array (1) and operable for high-speed serial data input and output of data in addition to random data access. The semiconductor memory device includes a single decoding circuit (5) triggering at least one gate for transferring data to be stored into or read from the memory cell array in a random data access mode and setting a single bit to a corresponding shift register (24) in the serial data input and output circuit in a serial data input and output operation mode. Preferably, the decoding circuit is operated only during a time for operatively connecting bit lines and latch circuits in the serial data input and output circuit in the serial data input and output operation mode.
    The serial data input and output circuit is operable independently from the memory cell array, except during the time for operatively connecting the bit lines and the latch circuits through transfer gates, for serially inputting data to or outputting data from the latch circuits through serial data bus by sequentially triggering the serial gates from a certain gate designated by the corresponding shift register in response to the decoding circuit.